Lines Matching refs:HOST_IRQ_STAT
541 * @irq_masked: HOST_IRQ_STAT value
544 * the HOST_IRQ_STAT register misses the edge interrupt
545 * when clearing of HOST_IRQ_STAT register and hardware
550 * 1. Read HOST_IRQ_STAT register and save the state.
551 * 2. Clear the HOST_IRQ_STAT register.
552 * 3. Read back the HOST_IRQ_STAT register.
553 * 4. If HOST_IRQ_STAT register equals to zero, then
558 * then update the state of HOST_IRQ_STAT saved in step 1.
569 if (!readl(hpriv->mmio + HOST_IRQ_STAT)) {
595 irq_stat = readl(mmio + HOST_IRQ_STAT);
604 * HOST_IRQ_STAT behaves as edge triggered latch meaning that
607 writel(irq_stat, mmio + HOST_IRQ_STAT);
663 writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
664 readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */