Lines Matching refs:val
180 u32 val;
183 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
184 val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
185 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
194 u32 val;
197 ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
201 calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
205 val = readl(tegra->sata_regs +
207 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
208 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
209 val |= calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
210 val |= calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
211 writel(val, tegra->sata_regs + SCFG_OFFSET +
214 val = readl(tegra->sata_regs +
216 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
217 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
218 val |= calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
219 val |= calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
220 writel(val, tegra->sata_regs + SCFG_OFFSET +
292 u32 val;
305 val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
306 val &= ~(SATA_FPCI_BAR5_START_MASK | SATA_FPCI_BAR5_ACCESS_TYPE);
307 val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
308 writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
311 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
312 val |= SATA_CONFIGURATION_0_EN_FPCI;
313 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
316 val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
317 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);
318 val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
319 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);
320 val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
321 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);
322 val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
323 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);
327 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
328 val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
329 val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
330 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
332 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
333 val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
336 val |= (T_SATA0_NVOOB_COMMA_CNT |
339 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
344 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
345 val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
346 val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
347 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
356 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
357 val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
359 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
360 val = T_SATA0_CFG_9_BASE_ADDRESS;
361 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
364 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
365 val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
366 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
368 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
369 val &=
372 val |= T_SATA0_BKDOOR_CC_CLASS_CODE | T_SATA0_BKDOOR_CC_PROG_IF;
373 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
375 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
376 val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
377 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
380 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
381 val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
385 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
391 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
392 val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
393 val |= T_SATA0_CFG_35_IDP_INDEX;
394 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
396 val = T_SATA0_AHCI_IDP1_DATA;
397 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
399 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
400 val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
402 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
405 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
406 val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
407 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
413 val = readl(tegra->sata_regs + SATA_INTR_MASK);
414 val |= SATA_INTR_MASK_IP_INT_MASK;
415 writel(val, tegra->sata_regs + SATA_INTR_MASK);