Lines Matching refs:reg_base
63 struct ccsr_ahci *reg_base;
173 void __iomem *reg_base = hpriv->mmio;
181 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
182 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
183 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
184 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
185 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
186 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
189 reg_base + LS1021A_AXICC_ADDR);
199 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
200 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
201 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
202 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
204 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
208 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
209 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
210 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
211 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
213 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
223 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
224 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
225 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
226 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
228 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
240 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
241 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
242 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
243 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
245 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
249 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
250 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
251 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
252 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
254 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);