Lines Matching refs:port
57 pr_info("no port info for ttyS%d\n", index);
74 if (synth_request_region(ser->port, 8)) {
77 __release_region(&ioport_resource, ser->port, 8);
78 err = synth_request_region(ser->port, 8);
80 pr_warn("Unable to allocate port at %x, errno %i",
81 ser->port, err);
89 outb(cval | UART_LCR_DLAB, ser->port + UART_LCR); /* set DLAB */
90 outb(quot & 0xff, ser->port + UART_DLL); /* LS of divisor */
91 outb(quot >> 8, ser->port + UART_DLM); /* MS of divisor */
92 outb(cval, ser->port + UART_LCR); /* reset DLAB */
95 outb(0, ser->port + UART_IER);
96 outb(UART_MCR_DTR | UART_MCR_RTS, ser->port + UART_MCR);
99 if (inb(ser->port + UART_LSR) == 0xff) {
100 synth_release_region(ser->port, 8);
106 speakup_info.port_tts = ser->port;
182 outb_p(0, ser->port);
184 outb_p('\r', ser->port);
188 pr_warn("ttyS%i is an invalid port\n", synth->ser);