Lines Matching refs:pirq
47 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
48 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
197 * ALI pirq entries are damn ugly, and completely undocumented.
198 * This has been figured out from pirq tables, and it's not a pretty
201 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
205 WARN_ON_ONCE(pirq > 16);
206 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
209 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
214 WARN_ON_ONCE(pirq > 16);
216 write_config_nybble(router, 0x48, pirq-1, val);
223 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
226 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
230 pci_read_config_byte(router, pirq, &x);
234 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
236 pci_write_config_byte(router, pirq, irq);
241 * The VIA pirq rules are nibble-based, like ALI,
245 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
247 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
250 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
252 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
257 * The VIA pirq rules are nibble-based, like ALI,
261 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
265 WARN_ON_ONCE(pirq > 5);
266 return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
269 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
273 WARN_ON_ONCE(pirq > 5);
274 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
279 * ITE 8330G pirq rules are nibble-based
283 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
287 WARN_ON_ONCE(pirq > 4);
288 return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
291 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
295 WARN_ON_ONCE(pirq > 4);
296 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
304 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
306 return read_config_nybble(router, 0xb8, pirq >> 4);
309 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
311 write_config_nybble(router, 0xb8, pirq >> 4, irq);
320 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
322 return read_config_nybble(router, 0x5C, (pirq-1)^1);
325 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
327 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
396 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
401 reg = pirq;
408 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
413 reg = pirq;
432 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
434 WARN_ON_ONCE(pirq >= 9);
435 if (pirq > 8) {
436 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
439 return read_config_nybble(router, 0x74, pirq-1);
442 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
444 WARN_ON_ONCE(pirq >= 9);
445 if (pirq > 8) {
446 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
449 write_config_nybble(router, 0x74, pirq-1, irq);
464 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
466 outb(pirq, 0xc00);
471 int pirq, int irq)
473 outb(pirq, 0xc00);
482 * The AMD756 pirq rules are nibble-based
486 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
490 if (pirq <= 4)
491 irq = read_config_nybble(router, 0x56, pirq - 1);
494 dev->vendor, dev->device, pirq, irq);
498 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
502 dev->vendor, dev->device, pirq, irq);
503 if (pirq <= 4)
504 write_config_nybble(router, 0x56, pirq - 1, irq);
511 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
513 outb(0x10 + ((pirq - 1) >> 1), 0x24);
514 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
517 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
521 outb(0x10 + ((pirq - 1) >> 1), 0x24);
523 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
530 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
885 int i, pirq, newirq;
913 pirq = info->irq[pin - 1].link;
915 if (!pirq) {
920 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs);
926 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
929 r->set(pirq_router_dev, dev, pirq, 11);
935 pirq = 0x68;
937 dev->irq = r->get(pirq_router_dev, dev, pirq);
965 if ((pirq & 0xf0) == 0xf0) {
966 irq = pirq & 0xf;
968 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
974 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
992 /* Update IRQ for all devices with the same pirq value */
1001 if (info->irq[pin - 1].link == pirq) {