Lines Matching refs:val
106 static inline u64 op_amd_randomize_ibs_op(u64 val)
124 val += (s8)(random >> 4);
126 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
128 return val;
135 u64 val, ctl;
144 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
145 oprofile_write_reserve(&entry, regs, val,
147 oprofile_add_data64(&entry, val);
149 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
150 oprofile_add_data64(&entry, val);
163 rdmsrl(MSR_AMD64_IBSOPRIP, val);
164 oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE,
166 oprofile_add_data64(&entry, val);
167 rdmsrl(MSR_AMD64_IBSOPDATA, val);
168 oprofile_add_data64(&entry, val);
169 rdmsrl(MSR_AMD64_IBSOPDATA2, val);
170 oprofile_add_data64(&entry, val);
171 rdmsrl(MSR_AMD64_IBSOPDATA3, val);
172 oprofile_add_data64(&entry, val);
173 rdmsrl(MSR_AMD64_IBSDCLINAD, val);
174 oprofile_add_data64(&entry, val);
175 rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
176 oprofile_add_data64(&entry, val);
178 rdmsrl(MSR_AMD64_IBSBRTARGET, val);
179 oprofile_add_data(&entry, (unsigned long)val);
192 u64 val;
206 val = ibs_config.max_cnt_fetch >> 4;
207 val = min(val, IBS_FETCH_MAX_CNT);
208 ibs_config.max_cnt_fetch = val << 4;
209 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
210 val |= IBS_FETCH_ENABLE;
211 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
215 val = ibs_config.max_cnt_op >> 4;
221 val = clamp(val, 0x0081ULL, 0xFF80ULL);
222 ibs_config.max_cnt_op = val << 4;
230 val += IBS_RANDOM_MAXCNT_OFFSET;
232 val = min(val, IBS_OP_MAX_CNT_EXT);
234 val = min(val, IBS_OP_MAX_CNT);
236 (val - IBS_RANDOM_MAXCNT_OFFSET) << 4;
238 val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT);
239 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
240 val |= IBS_OP_ENABLE;
241 ibs_state.ibs_op_ctl = val;
247 val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
248 wrmsrl(MSR_AMD64_IBSOPCTL, val);
271 u64 val;
279 rdmsrl(msrs->controls[i].addr, val);
280 val &= model->reserved;
281 val |= op_x86_get_ctrl(model, &counter_config[virt]);
282 wrmsrl(msrs->controls[i].addr, val);
336 u64 val;
352 rdmsrl(msrs->controls[i].addr, val);
353 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
355 val &= model->reserved;
356 wrmsrl(msrs->controls[i].addr, val);
374 rdmsrl(msrs->controls[i].addr, val);
375 val &= model->reserved;
376 val |= op_x86_get_ctrl(model, &counter_config[virt]);
377 wrmsrl(msrs->controls[i].addr, val);
384 u64 val;
391 rdmsrl(msrs->counters[i].addr, val);
393 if (val & OP_CTR_OVERFLOW)
407 u64 val;
413 rdmsrl(msrs->controls[i].addr, val);
414 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
415 wrmsrl(msrs->controls[i].addr, val);
423 u64 val;
433 rdmsrl(msrs->controls[i].addr, val);
434 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
435 wrmsrl(msrs->controls[i].addr, val);