Lines Matching refs:b3
37 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
38 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
44 #define EMIT3_off32(b1, b2, b3, off) \
45 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
46 #define EMIT4_off32(b1, b2, b3, b4, off) \
47 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
599 u8 b1, b2, b3;
610 b3 = 0xC0;
611 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
623 b3 = 0xC0;
624 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
816 u8 b2 = 0, b3 = 0;
881 * b3 holds 'normal' opcode, b2 short form only valid
886 b3 = 0xC0;
890 b3 = 0xE8;
894 b3 = 0xE0;
898 b3 = 0xC8;
902 b3 = 0xF0;
908 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
912 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1025 case BPF_LSH: b3 = 0xE0; break;
1026 case BPF_RSH: b3 = 0xE8; break;
1027 case BPF_ARSH: b3 = 0xF8; break;
1031 EMIT2(0xD1, add_1reg(b3, dst_reg));
1033 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1064 case BPF_LSH: b3 = 0xE0; break;
1065 case BPF_RSH: b3 = 0xE8; break;
1066 case BPF_ARSH: b3 = 0xF8; break;
1068 EMIT2(0xD3, add_1reg(b3, dst_reg));