Lines Matching defs:cache
2811 * Update real mode segment cache. It may be not up-to-date if sement
6233 * Software based L1D cache flush which is used when microcode providing
6234 * the cache control MSR is not loaded.
6236 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6239 * information but as all relevant affected CPUs have 32KiB L1D cache size
6289 /* Now fill the cache */
7207 u8 cache;
7229 cache = MTRR_TYPE_UNCACHABLE;
7235 cache = MTRR_TYPE_WRBACK;
7242 cache = MTRR_TYPE_WRBACK;
7244 cache = MTRR_TYPE_UNCACHABLE;
7248 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
7251 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;