Lines Matching refs:intercept
93 bool always; /* True if intercept is always on */
128 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
145 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
595 /* Set the shadow bitmaps to the desired intercept states */
708 * Set intercept permissions for all direct access MSRs again. They
1127 * We intercept those #GP and allow access to them anyway
1974 * On an #MC intercept the MCE handler is not called automatically in
1990 * VMCB is undefined after a SHUTDOWN intercept
2110 * If VGIF is enabled, the STGI intercept is only added to
2112 * Likewise, clear the VINTR intercept, we will set it
2130 * in use, we still rely on the VINTR intercept (rather than
2862 * For an INVPCID intercept:
3302 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3303 * get that intercept, this function will be called again though and
3304 * we'll get the vintr intercept. However, if the vGIF feature is
3617 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3621 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3877 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3880 icpt_info = x86_intercept_map[info->intercept];
3887 if (info->intercept == x86_intercept_cr_read)
3893 if (info->intercept == x86_intercept_cr_write)
3897 info->intercept == x86_intercept_clts)
3907 if (info->intercept == x86_intercept_lmsw) {
3925 if (info->intercept == x86_intercept_wrmsr)
3942 if (info->intercept == x86_intercept_in ||
3943 info->intercept == x86_intercept_ins) {
3952 if (info->intercept == x86_intercept_outs ||
3953 info->intercept == x86_intercept_ins)
4181 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4182 * To properly emulate the INIT intercept,