Lines Matching defs:val
385 u64 val;
391 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
395 val |= (1ULL << 47);
397 low = lower_32_bits(val);
398 high = upper_32_bits(val);
2322 unsigned long val)
2332 val &= ~SVM_CR0_SELECTIVE_MASK;
2334 if (cr0 ^ val) {
2347 unsigned long val;
2365 val = kvm_register_readl(&svm->vcpu, reg);
2366 trace_kvm_cr_write(cr, val);
2369 if (!check_selective_cr0_intercepted(svm, val))
2370 err = kvm_set_cr0(&svm->vcpu, val);
2376 err = kvm_set_cr3(&svm->vcpu, val);
2379 err = kvm_set_cr4(&svm->vcpu, val);
2382 err = kvm_set_cr8(&svm->vcpu, val);
2392 val = kvm_read_cr0(&svm->vcpu);
2395 val = svm->vcpu.arch.cr2;
2398 val = kvm_read_cr3(&svm->vcpu);
2401 val = kvm_read_cr4(&svm->vcpu);
2404 val = kvm_get_cr8(&svm->vcpu);
2411 kvm_register_writel(&svm->vcpu, reg, val);
2412 trace_kvm_cr_read(cr, val);
2420 unsigned long val;
2442 val = kvm_register_readl(&svm->vcpu, reg);
2443 kvm_set_dr(&svm->vcpu, dr - 16, val);
2447 kvm_get_dr(&svm->vcpu, dr, &val);
2448 kvm_register_writel(&svm->vcpu, reg, val);
3891 unsigned long cr0, val;
3905 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
3909 val &= 0xfUL;
3912 val |= X86_CR0_PE;
3915 if (cr0 ^ val)