Lines Matching refs:apic
78 struct kvm_lapic *apic = vcpu->arch.apic;
80 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
81 apic_test_vector(vector, apic->regs + APIC_IRR);
97 static inline int apic_enabled(struct kvm_lapic *apic)
99 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
109 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
111 return apic->vcpu->vcpu_id;
210 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
222 struct kvm_lapic *apic = vcpu->arch.apic;
232 xapic_id = kvm_xapic_id(apic);
233 x2apic_id = kvm_x2apic_id(apic);
236 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
238 new->phys_map[x2apic_id] = apic;
243 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
244 new->phys_map[xapic_id] = apic;
246 if (!kvm_apic_sw_enabled(apic))
249 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
251 if (apic_x2apic_mode(apic)) {
255 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
265 cluster[ffs(mask) - 1] = apic;
272 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty.
285 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
289 kvm_lapic_set_reg(apic, APIC_SPIV, val);
291 if (enabled != apic->sw_enabled) {
292 apic->sw_enabled = enabled;
298 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
303 kvm_make_request(KVM_REQ_APF_READY, apic->vcpu);
306 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
308 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
309 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
312 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
314 kvm_lapic_set_reg(apic, APIC_LDR, id);
315 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
318 static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val)
320 kvm_lapic_set_reg(apic, APIC_DFR, val);
321 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
329 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
333 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
335 kvm_lapic_set_reg(apic, APIC_ID, id);
336 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
337 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
340 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
342 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
345 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
347 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
350 static inline int apic_lvtt_period(struct kvm_lapic *apic)
352 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
355 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
357 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
367 struct kvm_lapic *apic = vcpu->arch.apic;
383 kvm_lapic_set_reg(apic, APIC_LVR, v);
455 struct kvm_lapic *apic = vcpu->arch.apic;
457 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
461 static inline int apic_search_irr(struct kvm_lapic *apic)
463 return find_highest_vector(apic->regs + APIC_IRR);
466 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
474 if (!apic->irr_pending)
477 result = apic_search_irr(apic);
483 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
487 vcpu = apic->vcpu;
491 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
493 apic_find_highest_irr(apic));
495 apic->irr_pending = false;
496 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
497 if (apic_search_irr(apic) != -1)
498 apic->irr_pending = true;
504 apic_clear_irr(vec, vcpu->arch.apic);
508 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
512 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
515 vcpu = apic->vcpu;
525 ++apic->isr_count;
526 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
532 apic->highest_isr_cache = vec;
536 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
544 if (!apic->isr_count)
546 if (likely(apic->highest_isr_cache != -1))
547 return apic->highest_isr_cache;
549 result = find_highest_vector(apic->regs + APIC_ISR);
555 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
558 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
561 vcpu = apic->vcpu;
572 apic_find_highest_isr(apic));
574 --apic->isr_count;
575 BUG_ON(apic->isr_count < 0);
576 apic->highest_isr_cache = -1;
587 return apic_find_highest_irr(vcpu->arch.apic);
591 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
598 struct kvm_lapic *apic = vcpu->arch.apic;
600 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
705 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
708 if (apic->vcpu->arch.apicv_active)
709 highest_irr = kvm_x86_ops.sync_pir_to_irr(apic->vcpu);
711 highest_irr = apic_find_highest_irr(apic);
717 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
722 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
723 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
724 isr = apic_find_highest_isr(apic);
734 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
739 static void apic_update_ppr(struct kvm_lapic *apic)
743 if (__apic_update_ppr(apic, &ppr) &&
744 apic_has_interrupt_for_ppr(apic, ppr) != -1)
745 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
750 apic_update_ppr(vcpu->arch.apic);
754 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
756 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
757 apic_update_ppr(apic);
760 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
762 return mda == (apic_x2apic_mode(apic) ?
766 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
768 if (kvm_apic_broadcast(apic, mda))
771 if (apic_x2apic_mode(apic))
772 return mda == kvm_x2apic_id(apic);
780 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
783 return mda == kvm_xapic_id(apic);
786 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
790 if (kvm_apic_broadcast(apic, mda))
793 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
795 if (apic_x2apic_mode(apic))
801 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
843 struct kvm_lapic *target = vcpu->arch.apic;
1065 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1070 struct kvm_vcpu *vcpu = apic->vcpu;
1083 if (unlikely(!apic_enabled(apic)))
1093 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1096 apic->regs + APIC_TMR);
1099 apic->regs + APIC_TMR);
1103 kvm_lapic_set_irr(vector, apic);
1132 apic->pending_events = (1UL << KVM_APIC_INIT);
1140 apic->sipi_vector = vector;
1143 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1213 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1215 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1218 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1223 if (!kvm_ioapic_handles_vector(apic, vector))
1227 if (irqchip_split(apic->vcpu->kvm)) {
1228 apic->vcpu->arch.pending_ioapic_eoi = vector;
1229 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1233 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1238 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1241 static int apic_set_eoi(struct kvm_lapic *apic)
1243 int vector = apic_find_highest_isr(apic);
1245 trace_kvm_eoi(apic, vector);
1254 apic_clear_isr(vector, apic);
1255 apic_update_ppr(apic);
1257 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1258 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1260 kvm_ioapic_send_eoi(apic, vector);
1261 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1271 struct kvm_lapic *apic = vcpu->arch.apic;
1273 trace_kvm_eoi(apic, vector);
1275 kvm_ioapic_send_eoi(apic, vector);
1276 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1280 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high)
1291 if (apic_x2apic_mode(apic))
1298 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1301 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1307 ASSERT(apic != NULL);
1310 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1311 apic->lapic_timer.period == 0)
1315 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1319 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1321 (APIC_BUS_CYCLE_NS * apic->divide_count));
1326 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1328 struct kvm_vcpu *vcpu = apic->vcpu;
1336 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1338 if (apic->vcpu->arch.tpr_access_reporting)
1339 __report_tpr_access(apic, write);
1342 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1354 if (apic_lvtt_tscdeadline(apic))
1357 val = apic_get_tmcct(apic);
1360 apic_update_ppr(apic);
1361 val = kvm_lapic_get_reg(apic, offset);
1364 report_tpr_access(apic, false);
1367 val = kvm_lapic_get_reg(apic, offset);
1383 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1414 if (!apic_x2apic_mode(apic))
1423 result = __apic_read(apic, offset & ~0xf);
1442 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1444 return addr >= apic->base_address &&
1445 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1451 struct kvm_lapic *apic = to_lapic(this);
1452 u32 offset = address - apic->base_address;
1454 if (!apic_mmio_in_range(apic, address))
1457 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1466 kvm_lapic_reg_read(apic, offset, len, data);
1471 static void update_divide_count(struct kvm_lapic *apic)
1475 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1478 apic->divide_count = 0x1 << (tmp2 & 0x7);
1481 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1488 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1491 if (apic->lapic_timer.period < min_period) {
1495 apic->vcpu->vcpu_id,
1496 apic->lapic_timer.period, min_period);
1497 apic->lapic_timer.period = min_period;
1502 static void cancel_hv_timer(struct kvm_lapic *apic);
1504 static void apic_update_lvtt(struct kvm_lapic *apic)
1506 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1507 apic->lapic_timer.timer_mode_mask;
1509 if (apic->lapic_timer.timer_mode != timer_mode) {
1510 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1512 hrtimer_cancel(&apic->lapic_timer.timer);
1514 if (apic->lapic_timer.hv_timer_in_use)
1515 cancel_hv_timer(apic);
1517 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1518 apic->lapic_timer.period = 0;
1519 apic->lapic_timer.tscdeadline = 0;
1521 apic->lapic_timer.timer_mode = timer_mode;
1522 limit_periodic_timer_frequency(apic);
1533 struct kvm_lapic *apic = vcpu->arch.apic;
1534 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1536 if (kvm_apic_hw_enabled(apic)) {
1538 void *bitmap = apic->regs + APIC_ISR;
1541 bitmap = apic->regs + APIC_IRR;
1551 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1572 struct kvm_lapic *apic = vcpu->arch.apic;
1573 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
1595 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1600 struct kvm_lapic *apic = vcpu->arch.apic;
1603 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1604 apic->lapic_timer.expired_tscdeadline = 0;
1606 apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline;
1612 adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta);
1618 vcpu->arch.apic->lapic_timer.expired_tscdeadline &&
1619 vcpu->arch.apic->lapic_timer.timer_advance_ns &&
1625 static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic)
1627 struct kvm_timer *ktimer = &apic->lapic_timer;
1629 kvm_apic_local_deliver(apic, APIC_LVTT);
1630 if (apic_lvtt_tscdeadline(apic)) {
1632 } else if (apic_lvtt_oneshot(apic)) {
1638 static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn)
1640 struct kvm_vcpu *vcpu = apic->vcpu;
1641 struct kvm_timer *ktimer = &apic->lapic_timer;
1643 if (atomic_read(&apic->lapic_timer.pending))
1646 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1651 kvm_apic_inject_pending_timer_irqs(apic);
1655 if (kvm_use_posted_timer_interrupt(apic->vcpu)) {
1663 if (vcpu->arch.apic->lapic_timer.expired_tscdeadline &&
1664 vcpu->arch.apic->lapic_timer.timer_advance_ns)
1666 kvm_apic_inject_pending_timer_irqs(apic);
1670 atomic_inc(&apic->lapic_timer.pending);
1676 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1678 struct kvm_timer *ktimer = &apic->lapic_timer;
1682 struct kvm_vcpu *vcpu = apic->vcpu;
1699 likely(ns > apic->lapic_timer.timer_advance_ns)) {
1704 apic_timer_expired(apic, false);
1709 static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict)
1711 return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count;
1714 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1719 apic->lapic_timer.period =
1720 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
1721 limit_periodic_timer_frequency(apic);
1724 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1730 apic->divide_count, old_divisor);
1732 apic->lapic_timer.tscdeadline +=
1733 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1734 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1735 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1738 static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg)
1745 apic->lapic_timer.period =
1746 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
1748 if (!apic->lapic_timer.period) {
1749 apic->lapic_timer.tscdeadline = 0;
1753 limit_periodic_timer_frequency(apic);
1754 deadline = apic->lapic_timer.period;
1756 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1758 deadline = tmict_to_ns(apic,
1759 kvm_lapic_get_reg(apic, count_reg));
1761 deadline = apic->lapic_timer.period;
1762 else if (unlikely(deadline > apic->lapic_timer.period)) {
1767 apic->vcpu->vcpu_id,
1769 kvm_lapic_get_reg(apic, count_reg),
1770 deadline, apic->lapic_timer.period);
1771 kvm_lapic_set_reg(apic, count_reg, 0);
1772 deadline = apic->lapic_timer.period;
1777 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1778 nsec_to_cycles(apic->vcpu, deadline);
1779 apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline);
1784 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1797 apic->lapic_timer.target_expiration =
1798 ktime_add_ns(apic->lapic_timer.target_expiration,
1799 apic->lapic_timer.period);
1800 delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1801 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1802 nsec_to_cycles(apic->vcpu, delta);
1805 static void start_sw_period(struct kvm_lapic *apic)
1807 if (!apic->lapic_timer.period)
1811 apic->lapic_timer.target_expiration)) {
1812 apic_timer_expired(apic, false);
1814 if (apic_lvtt_oneshot(apic))
1817 advance_periodic_target_expiration(apic);
1820 hrtimer_start(&apic->lapic_timer.timer,
1821 apic->lapic_timer.target_expiration,
1830 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1834 static void cancel_hv_timer(struct kvm_lapic *apic)
1837 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1838 kvm_x86_ops.cancel_hv_timer(apic->vcpu);
1839 apic->lapic_timer.hv_timer_in_use = false;
1842 static bool start_hv_timer(struct kvm_lapic *apic)
1844 struct kvm_timer *ktimer = &apic->lapic_timer;
1845 struct kvm_vcpu *vcpu = apic->vcpu;
1866 if (!apic_lvtt_period(apic)) {
1872 cancel_hv_timer(apic);
1874 apic_timer_expired(apic, false);
1875 cancel_hv_timer(apic);
1884 static void start_sw_timer(struct kvm_lapic *apic)
1886 struct kvm_timer *ktimer = &apic->lapic_timer;
1889 if (apic->lapic_timer.hv_timer_in_use)
1890 cancel_hv_timer(apic);
1891 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1894 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1895 start_sw_period(apic);
1896 else if (apic_lvtt_tscdeadline(apic))
1897 start_sw_tscdeadline(apic);
1898 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1901 static void restart_apic_timer(struct kvm_lapic *apic)
1905 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))
1908 if (!start_hv_timer(apic))
1909 start_sw_timer(apic);
1916 struct kvm_lapic *apic = vcpu->arch.apic;
1920 if (!apic->lapic_timer.hv_timer_in_use)
1923 apic_timer_expired(apic, false);
1924 cancel_hv_timer(apic);
1926 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1927 advance_periodic_target_expiration(apic);
1928 restart_apic_timer(apic);
1937 restart_apic_timer(vcpu->arch.apic);
1943 struct kvm_lapic *apic = vcpu->arch.apic;
1947 if (apic->lapic_timer.hv_timer_in_use)
1948 start_sw_timer(apic);
1955 struct kvm_lapic *apic = vcpu->arch.apic;
1957 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1958 restart_apic_timer(apic);
1961 static void __start_apic_timer(struct kvm_lapic *apic, u32 count_reg)
1963 atomic_set(&apic->lapic_timer.pending, 0);
1965 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1966 && !set_target_expiration(apic, count_reg))
1969 restart_apic_timer(apic);
1972 static void start_apic_timer(struct kvm_lapic *apic)
1974 __start_apic_timer(apic, APIC_TMICT);
1977 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1981 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1982 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1984 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1986 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1990 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1998 if (!apic_x2apic_mode(apic))
1999 kvm_apic_set_xapic_id(apic, val >> 24);
2005 report_tpr_access(apic, true);
2006 apic_set_tpr(apic, val & 0xff);
2010 apic_set_eoi(apic);
2014 if (!apic_x2apic_mode(apic))
2015 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
2021 if (!apic_x2apic_mode(apic))
2022 kvm_apic_set_dfr(apic, val | 0x0FFFFFFF);
2029 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
2031 apic_set_spiv(apic, val & mask);
2037 lvt_val = kvm_lapic_get_reg(apic,
2039 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
2042 apic_update_lvtt(apic);
2043 atomic_set(&apic->lapic_timer.pending, 0);
2051 kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2));
2052 kvm_lapic_set_reg(apic, APIC_ICR, val);
2056 if (!apic_x2apic_mode(apic))
2058 kvm_lapic_set_reg(apic, APIC_ICR2, val);
2062 apic_manage_nmi_watchdog(apic, val);
2072 if (!kvm_apic_sw_enabled(apic))
2078 kvm_lapic_set_reg(apic, reg, val);
2083 if (!kvm_apic_sw_enabled(apic))
2085 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
2086 kvm_lapic_set_reg(apic, APIC_LVTT, val);
2087 apic_update_lvtt(apic);
2091 if (apic_lvtt_tscdeadline(apic))
2094 hrtimer_cancel(&apic->lapic_timer.timer);
2095 kvm_lapic_set_reg(apic, APIC_TMICT, val);
2096 start_apic_timer(apic);
2100 uint32_t old_divisor = apic->divide_count;
2102 kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb);
2103 update_divide_count(apic);
2104 if (apic->divide_count != old_divisor &&
2105 apic->lapic_timer.period) {
2106 hrtimer_cancel(&apic->lapic_timer.timer);
2107 update_target_expiration(apic, old_divisor);
2108 restart_apic_timer(apic);
2113 if (apic_x2apic_mode(apic) && val != 0)
2122 if (!apic_x2apic_mode(apic) || (val & ~APIC_VECTOR_MASK))
2125 kvm_apic_send_ipi(apic, APIC_DEST_SELF | val, 0);
2132 kvm_recalculate_apic_map(apic->vcpu->kvm);
2141 struct kvm_lapic *apic = to_lapic(this);
2142 unsigned int offset = address - apic->base_address;
2145 if (!apic_mmio_in_range(apic, address))
2148 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
2166 kvm_lapic_reg_write(apic, offset & 0xff0, val);
2173 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
2185 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
2188 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
2194 struct kvm_lapic *apic = vcpu->arch.apic;
2196 if (!vcpu->arch.apic)
2199 hrtimer_cancel(&apic->lapic_timer.timer);
2204 if (!apic->sw_enabled)
2207 if (apic->regs)
2208 free_page((unsigned long)apic->regs);
2210 kfree(apic);
2220 struct kvm_lapic *apic = vcpu->arch.apic;
2222 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic))
2225 return apic->lapic_timer.tscdeadline;
2230 struct kvm_lapic *apic = vcpu->arch.apic;
2232 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic))
2235 hrtimer_cancel(&apic->lapic_timer.timer);
2236 apic->lapic_timer.tscdeadline = data;
2237 start_apic_timer(apic);
2242 apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4);
2249 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2257 struct kvm_lapic *apic = vcpu->arch.apic;
2259 if (!apic)
2267 if (!apic)
2273 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2279 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
2284 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2289 apic->base_address = apic->vcpu->arch.apic_base &
2293 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2299 struct kvm_lapic *apic = vcpu->arch.apic;
2303 apic->irr_pending = true;
2304 apic->isr_count = 1;
2306 apic->irr_pending = (apic_search_irr(apic) != -1);
2307 apic->isr_count = count_vectors(apic->regs + APIC_ISR);
2314 struct kvm_lapic *apic = vcpu->arch.apic;
2317 if (!apic)
2320 /* Stop the timer in case it's a reset to an active apic */
2321 hrtimer_cancel(&apic->lapic_timer.timer);
2326 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2328 kvm_apic_set_version(apic->vcpu);
2331 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2332 apic_update_lvtt(apic);
2335 kvm_lapic_set_reg(apic, APIC_LVT0,
2337 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2339 kvm_apic_set_dfr(apic, 0xffffffffU);
2340 apic_set_spiv(apic, 0xff);
2341 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2342 if (!apic_x2apic_mode(apic))
2343 kvm_apic_set_ldr(apic, 0);
2344 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2345 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2346 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2347 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2348 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2350 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2351 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2352 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2355 apic->highest_isr_cache = -1;
2356 update_divide_count(apic);
2357 atomic_set(&apic->lapic_timer.pending, 0);
2362 apic_update_ppr(apic);
2381 static bool lapic_is_periodic(struct kvm_lapic *apic)
2383 return apic_lvtt_period(apic);
2388 struct kvm_lapic *apic = vcpu->arch.apic;
2390 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2391 return atomic_read(&apic->lapic_timer.pending);
2396 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2398 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2402 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2407 r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL);
2409 kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED);
2417 struct kvm_lapic *apic = vcpu->arch.apic;
2419 if (apic)
2420 kvm_apic_local_deliver(apic, APIC_LVT0);
2431 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2433 apic_timer_expired(apic, true);
2435 if (lapic_is_periodic(apic)) {
2436 advance_periodic_target_expiration(apic);
2445 struct kvm_lapic *apic;
2449 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
2450 if (!apic)
2453 vcpu->arch.apic = apic;
2455 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
2456 if (!apic->regs) {
2457 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2461 apic->vcpu = vcpu;
2463 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2465 apic->lapic_timer.timer.function = apic_timer_fn;
2467 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
2470 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
2480 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2484 kfree(apic);
2485 vcpu->arch.apic = NULL;
2492 struct kvm_lapic *apic = vcpu->arch.apic;
2498 __apic_update_ppr(apic, &ppr);
2499 return apic_has_interrupt_for_ppr(apic, ppr);
2505 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2507 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2517 struct kvm_lapic *apic = vcpu->arch.apic;
2519 if (atomic_read(&apic->lapic_timer.pending) > 0) {
2520 kvm_apic_inject_pending_timer_irqs(apic);
2521 atomic_set(&apic->lapic_timer.pending, 0);
2528 struct kvm_lapic *apic = vcpu->arch.apic;
2541 apic_clear_irr(vector, apic);
2548 apic_update_ppr(apic);
2556 apic_set_isr(vector, apic);
2557 __apic_update_ppr(apic, &ppr);
2566 if (apic_x2apic_mode(vcpu->arch.apic)) {
2590 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2597 __apic_read(vcpu->arch.apic, APIC_TMCCT));
2604 struct kvm_lapic *apic = vcpu->arch.apic;
2609 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2616 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
2618 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
2622 apic_update_ppr(apic);
2623 hrtimer_cancel(&apic->lapic_timer.timer);
2624 apic_update_lvtt(apic);
2625 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2626 update_divide_count(apic);
2627 __start_apic_timer(apic, APIC_TMCCT);
2629 apic->highest_isr_cache = -1;
2633 apic_find_highest_irr(apic));
2635 apic_find_highest_isr(apic));
2654 timer = &vcpu->arch.apic->lapic_timer.timer;
2667 struct kvm_lapic *apic)
2692 vector = apic_set_eoi(apic);
2693 trace_kvm_pv_eoi(apic, vector);
2701 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2706 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2710 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2720 struct kvm_lapic *apic)
2724 apic->irr_pending ||
2726 apic->highest_isr_cache == -1 ||
2728 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2736 pv_eoi_set_pending(apic->vcpu);
2743 struct kvm_lapic *apic = vcpu->arch.apic;
2745 apic_sync_pv_eoi_to_guest(vcpu, apic);
2750 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2751 max_irr = apic_find_highest_irr(apic);
2754 max_isr = apic_find_highest_isr(apic);
2759 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2767 &vcpu->arch.apic->vapic_cache,
2775 vcpu->arch.apic->vapic_addr = vapic_addr;
2781 struct kvm_lapic *apic = vcpu->arch.apic;
2784 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2792 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2793 return kvm_lapic_reg_write(apic, reg, (u32)data);
2798 struct kvm_lapic *apic = vcpu->arch.apic;
2801 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2807 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2810 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2819 struct kvm_lapic *apic = vcpu->arch.apic;
2826 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2827 return kvm_lapic_reg_write(apic, reg, (u32)data);
2832 struct kvm_lapic *apic = vcpu->arch.apic;
2838 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2841 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2871 struct kvm_lapic *apic = vcpu->arch.apic;
2875 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2888 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2889 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2893 pe = xchg(&apic->pending_events, 0);
2896 if (kvm_vcpu_is_bsp(apic->vcpu))
2905 sipi_vector = apic->sipi_vector;