Lines Matching refs:x86_pmu
197 if (pmi && x86_pmu.version >= 4)
205 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask;
249 for (i = 0; i < x86_pmu.lbr_nr; i++)
250 wrmsrl(x86_pmu.lbr_from + i, 0);
257 for (i = 0; i < x86_pmu.lbr_nr; i++) {
258 wrmsrl(x86_pmu.lbr_from + i, 0);
259 wrmsrl(x86_pmu.lbr_to + i, 0);
260 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
261 wrmsrl(x86_pmu.lbr_info + i, 0);
268 wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr);
275 if (!x86_pmu.lbr_nr)
278 x86_pmu.lbr_reset();
291 rdmsrl(x86_pmu.lbr_tos, tos);
320 int lbr_format = x86_pmu.intel_cap.lbr_format;
365 wrmsrl(x86_pmu.lbr_from + idx, val);
370 wrmsrl(x86_pmu.lbr_to + idx, val);
375 wrmsrl(x86_pmu.lbr_info + idx, val);
385 rdmsrl(x86_pmu.lbr_from + idx, val);
397 rdmsrl(x86_pmu.lbr_to + idx, val);
409 rdmsrl(x86_pmu.lbr_info + idx, val);
442 bool need_info = x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO;
449 mask = x86_pmu.lbr_nr - 1;
455 for (; i < x86_pmu.lbr_nr; i++) {
459 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
463 wrmsrl(x86_pmu.lbr_tos, tos);
476 if (!entries[x86_pmu.lbr_nr - 1].from)
479 for (i = 0; i < x86_pmu.lbr_nr; i++) {
500 return x86_pmu.lbr_deep_c_reset && !rdlbr_from(0, NULL);
527 x86_pmu.lbr_restore(ctx);
534 bool need_info = x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO;
541 mask = x86_pmu.lbr_nr - 1;
543 for (i = 0; i < x86_pmu.lbr_nr; i++) {
561 for (i = 0; i < x86_pmu.lbr_nr; i++) {
567 if (i < x86_pmu.lbr_nr)
568 entries[x86_pmu.lbr_nr - 1].from = 0;
591 x86_pmu.lbr_save(ctx);
663 if (!x86_pmu.lbr_nr)
693 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0)
744 if (!x86_pmu.lbr_nr)
754 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0)
788 unsigned long mask = x86_pmu.lbr_nr - 1;
792 for (i = 0; i < x86_pmu.lbr_nr; i++) {
802 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
826 unsigned long mask = x86_pmu.lbr_nr - 1;
827 int lbr_format = x86_pmu.intel_cap.lbr_format;
831 int num = x86_pmu.lbr_nr;
896 if (abort && x86_pmu.lbr_double_abort && out > 0)
916 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) || !x86_pmu.lbr_br_type)
924 if (static_cpu_has(X86_FEATURE_ARCH_LBR) && !x86_pmu.lbr_mispred)
932 if (static_cpu_has(X86_FEATURE_ARCH_LBR) && !x86_pmu.lbr_mispred)
941 !(x86_pmu.lbr_timed_lbr && info & LBR_INFO_CYC_CNT_VALID))
955 for (i = 0; i < x86_pmu.lbr_nr; i++) {
1015 x86_pmu.lbr_read(cpuc);
1104 v = x86_pmu.lbr_sel_map[i];
1135 reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
1139 (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO))
1152 if (!x86_pmu.lbr_nr)
1165 if (x86_pmu.lbr_sel_map)
1567 x86_pmu.lbr_nr = 4;
1568 x86_pmu.lbr_tos = MSR_LBR_TOS;
1569 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1570 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1581 x86_pmu.lbr_nr = 16;
1582 x86_pmu.lbr_tos = MSR_LBR_TOS;
1583 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1584 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1586 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1587 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1601 x86_pmu.lbr_nr = 16;
1602 x86_pmu.lbr_tos = MSR_LBR_TOS;
1603 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1604 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1606 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1607 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
1628 x86_pmu.lbr_nr = 16;
1629 x86_pmu.lbr_tos = MSR_LBR_TOS;
1630 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1631 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1633 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1634 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1647 x86_pmu.lbr_nr = 32;
1648 x86_pmu.lbr_tos = MSR_LBR_TOS;
1649 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1650 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1651 x86_pmu.lbr_info = MSR_LBR_INFO_0;
1653 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1654 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1680 x86_pmu.lbr_nr = 8;
1681 x86_pmu.lbr_tos = MSR_LBR_TOS;
1682 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1683 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1694 x86_pmu.lbr_nr = 8;
1695 x86_pmu.lbr_tos = MSR_LBR_TOS;
1696 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1697 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1699 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1700 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1712 x86_pmu.lbr_nr = 8;
1713 x86_pmu.lbr_tos = MSR_LBR_TOS;
1714 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1715 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1717 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1718 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
1721 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP)
1722 x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS;
1733 x86_pmu.lbr_nr * sizeof(struct lbr_entry);
1776 x86_pmu.lbr_depth_mask = eax.split.lbr_depth_mask;
1777 x86_pmu.lbr_deep_c_reset = eax.split.lbr_deep_c_reset;
1778 x86_pmu.lbr_lip = eax.split.lbr_lip;
1779 x86_pmu.lbr_cpl = ebx.split.lbr_cpl;
1780 x86_pmu.lbr_filter = ebx.split.lbr_filter;
1781 x86_pmu.lbr_call_stack = ebx.split.lbr_call_stack;
1782 x86_pmu.lbr_mispred = ecx.split.lbr_mispred;
1783 x86_pmu.lbr_timed_lbr = ecx.split.lbr_timed_lbr;
1784 x86_pmu.lbr_br_type = ecx.split.lbr_br_type;
1785 x86_pmu.lbr_nr = lbr_nr;
1804 x86_pmu.lbr_from = MSR_ARCH_LBR_FROM_0;
1805 x86_pmu.lbr_to = MSR_ARCH_LBR_TO_0;
1806 x86_pmu.lbr_info = MSR_ARCH_LBR_INFO_0;
1809 if (!x86_pmu.lbr_cpl ||
1810 !x86_pmu.lbr_filter ||
1811 !x86_pmu.lbr_call_stack)
1814 if (!x86_pmu.lbr_cpl) {
1817 } else if (!x86_pmu.lbr_filter) {
1827 x86_pmu.lbr_ctl_mask = ARCH_LBR_CTL_MASK;
1828 x86_pmu.lbr_ctl_map = arch_lbr_ctl_map;
1830 if (!x86_pmu.lbr_cpl && !x86_pmu.lbr_filter)
1831 x86_pmu.lbr_ctl_map = NULL;
1833 x86_pmu.lbr_reset = intel_pmu_arch_lbr_reset;
1835 x86_pmu.lbr_save = intel_pmu_arch_lbr_xsaves;
1836 x86_pmu.lbr_restore = intel_pmu_arch_lbr_xrstors;
1837 x86_pmu.lbr_read = intel_pmu_arch_lbr_read_xsave;
1840 x86_pmu.lbr_save = intel_pmu_arch_lbr_save;
1841 x86_pmu.lbr_restore = intel_pmu_arch_lbr_restore;
1842 x86_pmu.lbr_read = intel_pmu_arch_lbr_read;
1862 int lbr_fmt = x86_pmu.intel_cap.lbr_format;
1864 lbr->nr = x86_pmu.lbr_nr;
1865 lbr->from = x86_pmu.lbr_from;
1866 lbr->to = x86_pmu.lbr_to;
1867 lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0;