Lines Matching defs:pbm
199 struct pci_pbm_info *pbm = dev_id;
200 unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;
201 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
220 pbm->name,
228 pbm->name,
232 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
233 printk("%s: UE Secondary errors [", pbm->name);
252 psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
259 struct pci_pbm_info *pbm = dev_id;
260 unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;
261 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
279 pbm->name,
290 pbm->name,
295 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
296 printk("%s: CE Secondary errors [", pbm->name);
313 static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
315 struct device_node *dp = pbm->op->dev.of_node;
317 unsigned long base = pbm->controller_regs;
321 if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
346 err = request_irq(op->archdata.irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
349 pbm->name, err);
356 err = request_irq(op->archdata.irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
359 pbm->name, err);
361 "SABRE_PCIERR", pbm);
364 pbm->name, err);
407 static void sabre_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
419 pbm->is_66mhz_capable = 1;
421 pbm->is_66mhz_capable = 0;
435 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
436 if (!pbm->pci_bus)
439 sabre_root_bus = pbm->pci_bus;
441 apb_init(pbm->pci_bus);
443 sabre_register_error_handlers(pbm);
446 static void sabre_pbm_init(struct pci_pbm_info *pbm,
449 psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE);
450 pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR;
451 pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR;
452 pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL;
453 sabre_scan_bus(pbm, &op->dev);
462 struct pci_pbm_info *pbm;
484 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
485 if (!pbm) {
496 pbm->iommu = iommu;
500 pbm->portid = upa_portid;
516 pbm->controller_regs = pr_regs[0].phys_addr;
522 upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
526 upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
531 pbm->controller_regs + SABRE_PCICTRL);
534 pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE;
562 err = psycho_iommu_init(pbm, tsbsize, vdma[0], dma_mask, SABRE_WRSYNC);
569 sabre_pbm_init(pbm, op);
571 pbm->next = pci_pbm_root;
572 pci_pbm_root = pbm;
574 dev_set_drvdata(&op->dev, pbm);
579 kfree(pbm->iommu);
582 kfree(pbm);