Lines Matching defs:data
184 unsigned int lane, unsigned int data)
191 /* Set write data */
192 pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
305 unsigned int data;
320 data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
321 data &= ~(PCI_EXP_FLAGS_TYPE << 16);
324 data |= PCI_EXP_TYPE_ENDPOINT << 20;
326 data |= PCI_EXP_TYPE_ROOT_PORT << 20;
328 data |= PCI_CAP_ID_EXP;
329 pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
331 /* Enable data link layer active state reporting */
335 data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
336 data &= ~PCI_EXP_LNKCTL_ASPMC;
337 data |= PCI_EXP_LNKCTL_ES | 1;
338 pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
341 data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
342 data &= ~PCI_EXP_SLTCAP_PSN;
343 data |= (port->index + 1) << 19;
344 pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
347 data = pci_read_reg(chan, SH4A_PCIETLCTLR);
348 data &= ~0x3f00;
349 data |= 0x32 << 8;
350 pci_write_reg(chan, data, SH4A_PCIETLCTLR);
354 * and enable MAC data scrambling.
356 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
357 data &= ~PCIEMACCTLR_SCR_DIS;
358 data |= (0xff << 16);
359 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
398 data = pci_read_reg(chan, SH4A_PCIETCTLR);
399 data |= 0x1;
400 pci_write_reg(chan, data, SH4A_PCIETCTLR);
406 data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
407 data |= PCIEDLINTENR_DLL_ACT_ENABLE;
408 pci_write_reg(chan, data, SH4A_PCIEDLINTENR);
410 /* Disable MAC data scrambling. */
411 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
412 data |= PCIEMACCTLR_SCR_DIS | (0xff << 16);
413 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
422 data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
423 data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
424 data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
426 pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
434 data = pci_read_reg(chan, SH4A_PCIEMACSR);
436 port->index, (data >> 20) & 0x3f);
500 static void __init sh7786_pcie_init_hw(void *data, async_cookie_t cookie)
502 struct sh7786_pcie_port *port = data;