Lines Matching defs:chan
155 static int __init phy_wait_for_ack(struct pci_channel *chan)
160 if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))
169 static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
174 if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)
183 static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr,
192 pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
193 pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
195 phy_wait_for_ack(chan);
198 pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
199 pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
201 phy_wait_for_ack(chan);
206 struct pci_channel *chan = port->hose;
241 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR);
261 struct pci_channel *chan = port->hose;
267 phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
268 phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
269 phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);
270 phy_write_reg(chan, 0x65, 0xf, 0x09070907);
271 phy_write_reg(chan, 0x66, 0xf, 0x00000010);
272 phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
273 phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
274 phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
277 phy_write_reg(chan, 0x67, 0x1, 0x00000400);
283 if (pci_read_reg(chan, SH4A_PCIEPHYSR))
294 struct pci_channel *chan = port->hose;
296 pci_write_reg(chan, 1, SH4A_PCIESRSTR);
297 pci_write_reg(chan, 0, SH4A_PCIETCTLR);
298 pci_write_reg(chan, 0, SH4A_PCIESRSTR);
299 pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
304 struct pci_channel *chan = port->hose;
317 pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI << 16, SH4A_PCIEIDSETR1);
320 data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
329 pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
332 pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
335 data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
338 pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
341 data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
344 pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
347 data = pci_read_reg(chan, SH4A_PCIETLCTLR);
350 pci_write_reg(chan, data, SH4A_PCIETLCTLR);
356 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
359 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
378 pci_write_reg(chan, memstart + SZ_512M, SH4A_PCIELAR1);
379 pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,
386 pci_write_reg(chan, 0, SH4A_PCIELAR1);
387 pci_write_reg(chan, 0, SH4A_PCIELAMR1);
394 pci_write_reg(chan, memstart, SH4A_PCIELAR0);
395 pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);
398 data = pci_read_reg(chan, SH4A_PCIETCTLR);
400 pci_write_reg(chan, data, SH4A_PCIETCTLR);
406 data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
408 pci_write_reg(chan, data, SH4A_PCIEDLINTENR);
411 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
413 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
420 ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
422 data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
426 pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
428 pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
429 pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
434 data = pci_read_reg(chan, SH4A_PCIEMACSR);
441 for (i = win = 0; i < chan->nr_resources; i++) {
442 struct resource *res = chan->resources + i;
456 pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
464 pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win));
466 pci_write_reg(chan, upper_32_bits(res->start),
468 pci_write_reg(chan, lower_32_bits(res->start),
475 pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win));