Lines Matching refs:x00

41 	{ S1DREG_MISC,			0x00 },
42 { S1DREG_COM_DISP_MODE, 0x00 },
43 { S1DREG_GPIO_CNF0, 0x00 },
44 { S1DREG_GPIO_CNF1, 0x00 },
45 { S1DREG_GPIO_CTL0, 0x00 },
46 { S1DREG_GPIO_CTL1, 0x00 },
53 { S1DREG_SDRAM_TC0, 0x00 },
57 { S1DREG_MOD_RATE, 0x00 },
64 { S1DREG_LCD_NDISP_VPER, 0x00 },
68 { S1DREG_LCD_MISC, 0x00 },
69 { S1DREG_LCD_DISP_START0, 0x00 },
70 { S1DREG_LCD_DISP_START1, 0x00 },
71 { S1DREG_LCD_DISP_START2, 0x00 },
74 { S1DREG_LCD_PIX_PAN, 0x00 },
75 { S1DREG_LCD_DISP_FIFO_HTC, 0x00 },
76 { S1DREG_LCD_DISP_FIFO_LTC, 0x00 },
84 { S1DREG_CRT_VRTC_START, 0x00 },
88 { S1DREG_CRT_DISP_START0, 0x00 },
89 { S1DREG_CRT_DISP_START1, 0x00 },
90 { S1DREG_CRT_DISP_START2, 0x00 },
93 { S1DREG_CRT_PIX_PAN, 0x00 },
94 { S1DREG_CRT_DISP_FIFO_HTC, 0x00 },
95 { S1DREG_CRT_DISP_FIFO_LTC, 0x00 },
96 { S1DREG_LCD_CUR_CTL, 0x00 },
98 { S1DREG_LCD_CUR_XPOS0, 0x00 },
99 { S1DREG_LCD_CUR_XPOS1, 0x00 },
100 { S1DREG_LCD_CUR_YPOS0, 0x00 },
101 { S1DREG_LCD_CUR_YPOS1, 0x00 },
102 { S1DREG_LCD_CUR_BCTL0, 0x00 },
103 { S1DREG_LCD_CUR_GCTL0, 0x00 },
104 { S1DREG_LCD_CUR_RCTL0, 0x00 },
108 { S1DREG_LCD_CUR_FIFO_HTC, 0x00 },
109 { S1DREG_CRT_CUR_CTL, 0x00 },
111 { S1DREG_CRT_CUR_XPOS0, 0x00 },
112 { S1DREG_CRT_CUR_XPOS1, 0x00 },
113 { S1DREG_CRT_CUR_YPOS0, 0x00 },
114 { S1DREG_CRT_CUR_YPOS1, 0x00 },
115 { S1DREG_CRT_CUR_BCTL0, 0x00 },
116 { S1DREG_CRT_CUR_GCTL0, 0x00 },
117 { S1DREG_CRT_CUR_RCTL0, 0x00 },
121 { S1DREG_CRT_CUR_FIFO_HTC, 0x00 },
122 { S1DREG_BBLT_CTL0, 0x00 },
123 { S1DREG_BBLT_CTL1, 0x00 },
124 { S1DREG_BBLT_CC_EXP, 0x00 },
125 { S1DREG_BBLT_OP, 0x00 },
126 { S1DREG_BBLT_SRC_START0, 0x00 },
127 { S1DREG_BBLT_SRC_START1, 0x00 },
128 { S1DREG_BBLT_SRC_START2, 0x00 },
129 { S1DREG_BBLT_DST_START0, 0x00 },
130 { S1DREG_BBLT_DST_START1, 0x00 },
131 { S1DREG_BBLT_DST_START2, 0x00 },
132 { S1DREG_BBLT_MEM_OFF0, 0x00 },
133 { S1DREG_BBLT_MEM_OFF1, 0x00 },
134 { S1DREG_BBLT_WIDTH0, 0x00 },
135 { S1DREG_BBLT_WIDTH1, 0x00 },
136 { S1DREG_BBLT_HEIGHT0, 0x00 },
137 { S1DREG_BBLT_HEIGHT1, 0x00 },
138 { S1DREG_BBLT_BGC0, 0x00 },
139 { S1DREG_BBLT_BGC1, 0x00 },
140 { S1DREG_BBLT_FGC0, 0x00 },
141 { S1DREG_BBLT_FGC1, 0x00 },
142 { S1DREG_LKUP_MODE, 0x00 },
143 { S1DREG_LKUP_ADDR, 0x00 },
145 { S1DREG_PS_STATUS, 0x00 },
146 { S1DREG_CPU2MEM_WDOGT, 0x00 },