Lines Matching refs:event
23 * set in the Event Mask Registers (EMRs). When a hardware event is
26 * event.
45 #define ESR_BASE 0x005f6900 /* Base event status register */
46 #define EMR_BASE 0x005f6910 /* Base event mask register */
49 * Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
50 * 1 = 0x6920, 2 = 0x6930; also determine the event offset.
52 #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
54 /* Return the hardware event's bit position within the EMR/ESR */
55 #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
59 * (logically mapped to the corresponding bit for the hardware event).
62 /* Disable the hardware event by masking its bit in its EMR */
74 /* Enable the hardware event by setting its bit in its EMR */
86 /* Acknowledge a hardware event by writing its bit back to its ESR */
103 * Map the hardware event indicated by the processor IRQ to a virtual IRQ.
130 /* Now scan and find the first set bit as the event to map */