Lines Matching refs:VS
742 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
744 #define VS VD
4799 {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4879 {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4903 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4955 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4987 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5027 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5437 {"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5470 {"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5542 {"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5735 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5888 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
5926 {"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5928 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
5944 {"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5982 {"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6024 {"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6064 {"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6142 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6181 {"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6187 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6216 {"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6248 {"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6672 {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6673 {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},