Lines Matching refs:FSL
867 /* Xilinx FSL related masks and macros */
868 #define FSL FCRT + 1
873 #define URT FSL + 1
3298 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3321 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3332 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3334 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3363 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3368 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3396 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3425 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},