Lines Matching refs:xd
196 static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
200 if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
204 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
207 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
208 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
210 val = in_be64(xd->eoi_mmio + offset);
215 static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
218 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
221 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
222 xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
224 out_be64(xd->eoi_mmio + offset, data);
291 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
292 u64 val = xive_esb_read(xd, XIVE_ESB_GET);
295 xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ',
296 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ',
297 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ',
365 static void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
367 xd->stale_p = false;
369 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
370 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
371 else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {
398 if (xd->flags & XIVE_IRQ_FLAG_LSI)
399 xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
401 eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
405 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
406 out_be64(xd->trig_mmio, 0);
414 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
425 !(xd->flags & XIVE_IRQ_NO_EOI))
426 xive_do_source_eoi(irqd_to_hwirq(d), xd);
428 xd->stale_p = true;
434 xd->saved_p = false;
445 static void xive_do_source_set_mask(struct xive_irq_data *xd,
459 val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
460 if (!xd->stale_p && !!(val & XIVE_ESB_VAL_P))
461 xd->saved_p = true;
462 xd->stale_p = false;
463 } else if (xd->saved_p) {
464 xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
465 xd->saved_p = false;
467 xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
468 xd->stale_p = false;
572 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
580 if (xd->src_chip != XIVE_INVALID_CHIP_ID &&
585 if (xc->chip_id == xd->src_chip)
605 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
609 xd->saved_p = false;
610 xd->stale_p = false;
639 xd->target = target;
652 xive_do_source_set_mask(xd, false);
660 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
666 if (WARN_ON(xd->target == XIVE_INVALID_TARGET))
670 xive_do_source_set_mask(xd, true);
677 get_hard_smp_processor_id(xd->target),
680 xive_dec_target_count(xd->target);
681 xd->target = XIVE_INVALID_TARGET;
686 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
688 pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd);
696 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
699 get_hard_smp_processor_id(xd->target),
704 xive_do_source_set_mask(xd, false);
709 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
711 pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd);
719 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
722 get_hard_smp_processor_id(xd->target),
727 xive_do_source_set_mask(xd, true);
734 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
753 if (xd->target != XIVE_INVALID_TARGET &&
754 cpu_online(xd->target) &&
755 cpumask_test_cpu(xd->target, cpumask))
769 old_target = xd->target;
785 xd->target = target;
796 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
823 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) {
827 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge");
835 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
838 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI))
845 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
853 xive_do_source_eoi(0, xd);
864 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
873 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW)
884 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
885 if (!xd->stale_p) {
886 xd->saved_p = !!(pq & XIVE_ESB_VAL_P);
887 xd->stale_p = !xd->saved_p;
891 if (xd->target == XIVE_INVALID_TARGET) {
896 WARN_ON(xd->saved_p);
916 if (xd->saved_p) {
917 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
935 if (xd->target == XIVE_INVALID_TARGET) {
936 xive_do_source_set_mask(xd, true);
957 get_hard_smp_processor_id(xd->target),
974 if (!xd->saved_p)
975 xive_do_source_eoi(hw_irq, xd);
985 struct xive_irq_data *xd = irq_data_get_irq_handler_data(data);
990 pq = xive_esb_read(xd, XIVE_ESB_GET);
999 *state = (pq != XIVE_ESB_INVALID) && !xd->stale_p &&
1000 (xd->saved_p || (!!(pq & XIVE_ESB_VAL_P) &&
1028 void xive_cleanup_irq_data(struct xive_irq_data *xd)
1030 if (xd->eoi_mmio) {
1031 unmap_kernel_range((unsigned long)xd->eoi_mmio,
1032 1u << xd->esb_shift);
1033 iounmap(xd->eoi_mmio);
1034 if (xd->eoi_mmio == xd->trig_mmio)
1035 xd->trig_mmio = NULL;
1036 xd->eoi_mmio = NULL;
1038 if (xd->trig_mmio) {
1039 unmap_kernel_range((unsigned long)xd->trig_mmio,
1040 1u << xd->esb_shift);
1041 iounmap(xd->trig_mmio);
1042 xd->trig_mmio = NULL;
1049 struct xive_irq_data *xd;
1052 xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL);
1053 if (!xd)
1055 rc = xive_ops->populate_irq_data(hw, xd);
1057 kfree(xd);
1060 xd->target = XIVE_INVALID_TARGET;
1061 irq_set_handler_data(virq, xd);
1070 xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
1077 struct xive_irq_data *xd = irq_get_handler_data(virq);
1079 if (!xd)
1082 xive_cleanup_irq_data(xd);
1083 kfree(xd);
1091 struct xive_irq_data *xd;
1098 xd = &xc->ipi_data;
1099 if (WARN_ON(!xd->trig_mmio))
1101 out_be64(xd->trig_mmio, 0);
1424 struct xive_irq_data *xd;
1444 xd = irq_desc_get_handler_data(desc);
1449 xd->saved_p = false;
1455 if (xd->flags & XIVE_IRQ_FLAG_LSI)
1456 xive_do_source_eoi(irqd_to_hwirq(d), xd);
1616 struct xive_irq_data *xd;
1631 xd = irq_data_get_irq_handler_data(d);
1632 val = xive_esb_read(xd, XIVE_ESB_GET);
1634 xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ',
1635 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ',
1636 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ',