Lines Matching refs:mpic
2 * arch/powerpc/kernel/mpic.c
39 #include <asm/mpic.h>
42 #include "mpic.h"
51 .name = "mpic",
52 .dev_name = "mpic",
56 static struct mpic *mpics;
57 static struct mpic *mpic_primary;
150 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
158 static inline unsigned int mpic_processor_id(struct mpic *mpic)
162 if (!(mpic->flags & MPIC_SECONDARY))
210 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
212 enum mpic_reg_type type = mpic->reg_type;
216 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
218 return _mpic_read(type, &mpic->gregs, offset);
221 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
226 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
229 static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
235 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
237 unsigned int offset = mpic_tm_offset(mpic, tm) +
240 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
243 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
245 unsigned int offset = mpic_tm_offset(mpic, tm) +
248 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
251 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
253 unsigned int cpu = mpic_processor_id(mpic);
255 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
258 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
260 unsigned int cpu = mpic_processor_id(mpic);
262 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
265 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
267 unsigned int isu = src_no >> mpic->isu_shift;
268 unsigned int idx = src_no & mpic->isu_mask;
271 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
276 mpic->isu_reg0_shadow[src_no];
281 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
284 unsigned int isu = src_no >> mpic->isu_shift;
285 unsigned int idx = src_no & mpic->isu_mask;
287 _mpic_write(mpic->reg_type, &mpic->isus[isu],
292 mpic->isu_reg0_shadow[src_no] =
297 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
298 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
299 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
300 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
301 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
302 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
303 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
304 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
305 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
306 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
314 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
323 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
326 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
327 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
331 static inline void mpic_map(struct mpic *mpic,
335 if (mpic->flags & MPIC_USES_DCR)
336 _mpic_map_dcr(mpic, rb, offset, size);
338 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
349 static void __init mpic_test_broken_ipi(struct mpic *mpic)
353 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
354 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
357 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
358 mpic->flags |= MPIC_BROKEN_IPI;
367 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
369 if (source >= 128 || !mpic->fixups)
371 return mpic->fixups[source].base != NULL;
375 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
377 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
384 raw_spin_lock(&mpic->fixup_lock);
387 raw_spin_unlock(&mpic->fixup_lock);
391 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
394 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
403 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
411 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
416 mpic->save_data[source].fixup_data = tmp | 1;
420 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
422 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
432 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
437 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
442 mpic->save_data[source].fixup_data = tmp & ~1;
447 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
475 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
483 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
490 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
514 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
526 mpic->fixups[irq].index = i;
527 mpic->fixups[irq].base = base;
530 mpic->fixups[irq].applebase = devbase + 0x60;
532 mpic->fixups[irq].applebase = NULL;
534 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
539 static void __init mpic_scan_ht_pics(struct mpic *mpic)
544 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
547 mpic->fixups = kcalloc(128, sizeof(*mpic->fixups), GFP_KERNEL);
548 BUG_ON(mpic->fixups == NULL);
551 raw_spin_lock_init(&mpic->fixup_lock);
579 mpic_scan_ht_pic(mpic, devbase, devfn, l);
580 mpic_scan_ht_msi(mpic, devbase, devfn);
591 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
596 static void __init mpic_scan_ht_pics(struct mpic *mpic)
602 /* Find an mpic associated with a given linux interrupt */
603 static struct mpic *mpic_find(unsigned int irq)
612 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
614 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
618 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
620 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
635 /* Get the mpic structure from the IPI number */
636 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
642 /* Get the mpic structure from the irq number */
643 static inline struct mpic * mpic_from_irq(unsigned int irq)
648 /* Get the mpic structure from the irq data */
649 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
655 static inline void mpic_eoi(struct mpic *mpic)
668 struct mpic *mpic = mpic_from_irq_data(d);
671 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
689 struct mpic *mpic = mpic_from_irq_data(d);
692 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
710 struct mpic *mpic = mpic_from_irq_data(d);
713 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
720 mpic_eoi(mpic);
727 struct mpic *mpic = mpic_from_irq_data(d);
733 mpic_ht_end_irq(mpic, src);
738 struct mpic *mpic = mpic_from_irq_data(d);
742 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
749 struct mpic *mpic = mpic_from_irq_data(d);
752 mpic_shutdown_ht_interrupt(mpic, src);
758 struct mpic *mpic = mpic_from_irq_data(d);
762 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
770 mpic_ht_end_irq(mpic, src);
771 mpic_eoi(mpic);
779 struct mpic *mpic = mpic_from_ipi(d);
780 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
782 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
793 struct mpic *mpic = mpic_from_ipi(d);
800 mpic_eoi(mpic);
807 struct mpic *mpic = mpic_from_irq_data(d);
808 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
810 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
817 struct mpic *mpic = mpic_from_irq_data(d);
818 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
827 struct mpic *mpic = mpic_from_irq_data(d);
830 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
846 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
869 struct mpic *mpic = mpic_from_irq_data(d);
873 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
874 mpic, d->irq, src, flow_type);
876 if (src >= mpic->num_sources)
905 WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
912 if (mpic_is_ht_interrupt(mpic, src))
916 vecpri = mpic_type_to_vecpri(mpic, flow_type);
929 struct mpic *mpic = mpic_from_irq(virq);
933 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
934 mpic, virq, src, vector);
936 if (src >= mpic->num_sources)
947 struct mpic *mpic = mpic_from_irq(virq);
950 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
951 mpic, virq, src, cpuid);
953 if (src >= mpic->num_sources)
995 /* Exact match, unless mpic node is NULL */
1003 struct mpic *mpic = h->host_data;
1006 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1008 if (hw == mpic->spurious_vec)
1010 if (mpic->protected && test_bit(hw, mpic->protected)) {
1011 pr_warn("mpic: Mapping of source 0x%x failed, source protected by firmware !\n",
1017 else if (hw >= mpic->ipi_vecs[0]) {
1018 WARN_ON(mpic->flags & MPIC_SECONDARY);
1020 DBG("mpic: mapping as IPI\n");
1021 irq_set_chip_data(virq, mpic);
1022 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1028 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1029 WARN_ON(mpic->flags & MPIC_SECONDARY);
1031 DBG("mpic: mapping as timer\n");
1032 irq_set_chip_data(virq, mpic);
1033 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1038 if (mpic_map_error_int(mpic, virq, hw))
1041 if (hw >= mpic->num_sources) {
1042 pr_warn("mpic: Mapping of source 0x%x failed, source out of range !\n",
1047 mpic_msi_reserve_hwirq(mpic, hw);
1050 chip = &mpic->hc_irq;
1054 if (mpic_is_ht_interrupt(mpic, hw))
1055 chip = &mpic->hc_ht_irq;
1058 DBG("mpic: mapping to irq chip @%p\n", chip);
1060 irq_set_chip_data(virq, mpic);
1070 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1074 cpu = mpic_processor_id(mpic);
1090 struct mpic *mpic = h->host_data;
1099 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1105 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1111 if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1114 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1117 *out_hwirq = mpic->err_int_vecs[intspec[3]];
1121 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1124 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1127 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1130 *out_hwirq = mpic->timer_vecs[intspec[0]];
1158 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1168 struct mpic *mpic = irq_desc_get_handler_data(desc);
1171 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1173 virq = mpic_get_one_irq(mpic);
1186 static u32 fsl_mpic_get_version(struct mpic *mpic)
1190 if (!(mpic->flags & MPIC_FSL))
1193 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1205 struct mpic *mpic = mpic_primary;
1207 if (mpic)
1208 return fsl_mpic_get_version(mpic);
1213 struct mpic * __init mpic_alloc(struct device_node *node,
1221 struct mpic *mpic;
1267 if (of_device_is_compatible(node, "fsl,mpic")) {
1273 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1274 if (mpic == NULL)
1277 mpic->name = name;
1278 mpic->node = node;
1279 mpic->paddr = phys_addr;
1280 mpic->flags = flags;
1282 mpic->hc_irq = mpic_irq_chip;
1283 mpic->hc_irq.name = name;
1284 if (!(mpic->flags & MPIC_SECONDARY))
1285 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1287 mpic->hc_ht_irq = mpic_irq_ht_chip;
1288 mpic->hc_ht_irq.name = name;
1289 if (!(mpic->flags & MPIC_SECONDARY))
1290 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1294 mpic->hc_ipi = mpic_ipi_chip;
1295 mpic->hc_ipi.name = name;
1298 mpic->hc_tm = mpic_tm_chip;
1299 mpic->hc_tm.name = name;
1301 mpic->num_sources = 0; /* so far */
1303 if (mpic->flags & MPIC_LARGE_VECTORS)
1308 mpic->timer_vecs[0] = intvec_top - 12;
1309 mpic->timer_vecs[1] = intvec_top - 11;
1310 mpic->timer_vecs[2] = intvec_top - 10;
1311 mpic->timer_vecs[3] = intvec_top - 9;
1312 mpic->timer_vecs[4] = intvec_top - 8;
1313 mpic->timer_vecs[5] = intvec_top - 7;
1314 mpic->timer_vecs[6] = intvec_top - 6;
1315 mpic->timer_vecs[7] = intvec_top - 5;
1316 mpic->ipi_vecs[0] = intvec_top - 4;
1317 mpic->ipi_vecs[1] = intvec_top - 3;
1318 mpic->ipi_vecs[2] = intvec_top - 2;
1319 mpic->ipi_vecs[3] = intvec_top - 1;
1320 mpic->spurious_vec = intvec_top;
1323 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1327 mpic->protected = kcalloc(mapsize, sizeof(long), GFP_KERNEL);
1328 BUG_ON(mpic->protected == NULL);
1332 __set_bit(psrc[i], mpic->protected);
1337 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1341 if (mpic->flags & MPIC_BIG_ENDIAN)
1342 mpic->reg_type = mpic_access_mmio_be;
1344 mpic->reg_type = mpic_access_mmio_le;
1351 if (mpic->flags & MPIC_USES_DCR)
1352 mpic->reg_type = mpic_access_dcr;
1354 BUG_ON(mpic->flags & MPIC_USES_DCR);
1358 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1359 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1361 if (mpic->flags & MPIC_FSL) {
1369 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1372 fsl_version = fsl_mpic_get_version(mpic);
1388 ret = mpic_setup_error_int(mpic, intvec_top - 13);
1404 * an "fsl,mpic" compatible at all. This will be the case
1418 if (!(mpic->flags & MPIC_NO_RESET)) {
1419 printk(KERN_DEBUG "mpic: Resetting\n");
1420 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1421 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1423 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1429 if (mpic->flags & MPIC_ENABLE_COREINT)
1430 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1431 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1434 if (mpic->flags & MPIC_ENABLE_MCK)
1435 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1436 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1449 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1458 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1470 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1477 mpic->num_sources = isu_size;
1478 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1483 mpic->isu_size = isu_size;
1484 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1485 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1487 mpic->irqhost = irq_domain_add_linear(mpic->node,
1489 &mpic_host_ops, mpic);
1495 if (mpic->irqhost == NULL)
1513 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1515 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1516 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1517 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1519 mpic->next = mpics;
1520 mpics = mpic;
1522 if (!(mpic->flags & MPIC_SECONDARY)) {
1523 mpic_primary = mpic;
1524 irq_set_default_host(mpic->irqhost);
1527 return mpic;
1534 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1537 unsigned int isu_first = isu_num * mpic->isu_size;
1541 mpic_map(mpic,
1542 paddr, &mpic->isus[isu_num], 0,
1543 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1545 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1546 mpic->num_sources = isu_first + mpic->isu_size;
1549 void __init mpic_init(struct mpic *mpic)
1554 BUG_ON(mpic->num_sources == 0);
1556 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1561 if (mpic->flags & MPIC_FSL) {
1562 u32 version = fsl_mpic_get_version(mpic);
1576 unsigned int offset = mpic_tm_offset(mpic, i);
1578 mpic_write(mpic->tmregs,
1581 mpic_write(mpic->tmregs,
1585 (mpic->timer_vecs[0] + i));
1589 mpic_test_broken_ipi(mpic);
1594 (mpic->ipi_vecs[0] + i));
1597 /* Do the HT PIC fixups on U3 broken mpic */
1598 DBG("MPIC flags: %x\n", mpic->flags);
1599 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1600 mpic_scan_ht_pics(mpic);
1601 mpic_u3msi_init(mpic);
1604 mpic_pasemi_msi_init(mpic);
1606 cpu = mpic_processor_id(mpic);
1608 if (!(mpic->flags & MPIC_NO_RESET)) {
1609 for (i = 0; i < mpic->num_sources; i++) {
1615 if (mpic->protected && test_bit(i, mpic->protected))
1624 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1627 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1628 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1629 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1632 if (mpic->flags & MPIC_NO_BIAS)
1633 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1634 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1641 /* allocate memory to save mpic state */
1642 mpic->save_data = kmalloc_array(mpic->num_sources,
1643 sizeof(*mpic->save_data),
1645 BUG_ON(mpic->save_data == NULL);
1649 if (mpic->flags & MPIC_SECONDARY) {
1650 int virq = irq_of_parse_and_map(mpic->node, 0);
1653 mpic->node, virq);
1654 irq_set_handler_data(virq, mpic);
1659 /* FSL mpic error interrupt initialization */
1660 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1661 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1666 struct mpic *mpic = mpic_find(irq);
1671 if (!mpic)
1675 if (mpic_is_ipi(mpic, src)) {
1676 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1678 mpic_ipi_write(src - mpic->ipi_vecs[0],
1680 } else if (mpic_is_tm(mpic, src)) {
1681 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1683 mpic_tm_write(src - mpic->timer_vecs[0],
1697 struct mpic *mpic = mpic_primary;
1702 BUG_ON(mpic == NULL);
1704 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1708 /* let the mpic know we want intrs. default affinity is 0xffffffff
1713 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
1714 for (i = 0; i < mpic->num_sources ; i++)
1728 struct mpic *mpic = mpic_primary;
1735 struct mpic *mpic = mpic_primary;
1743 struct mpic *mpic = mpic_primary;
1748 BUG_ON(mpic == NULL);
1750 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1753 /* let the mpic know we don't want intrs. */
1754 for (i = 0; i < mpic->num_sources ; i++)
1763 mpic_eoi(mpic);
1769 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1775 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1777 if (unlikely(src == mpic->spurious_vec)) {
1778 if (mpic->flags & MPIC_SPV_EOI)
1779 mpic_eoi(mpic);
1782 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1784 mpic->name, (int)src);
1785 mpic_eoi(mpic);
1789 return irq_linear_revmap(mpic->irqhost, src);
1792 unsigned int mpic_get_one_irq(struct mpic *mpic)
1794 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1799 struct mpic *mpic = mpic_primary;
1801 BUG_ON(mpic == NULL);
1803 return mpic_get_one_irq(mpic);
1809 struct mpic *mpic = mpic_primary;
1812 BUG_ON(mpic == NULL);
1816 if (unlikely(src == mpic->spurious_vec)) {
1817 if (mpic->flags & MPIC_SPV_EOI)
1818 mpic_eoi(mpic);
1821 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1823 mpic->name, (int)src);
1827 return irq_linear_revmap(mpic->irqhost, src);
1835 struct mpic *mpic = mpic_primary;
1837 BUG_ON(mpic == NULL);
1839 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1845 struct mpic *mpic = mpic_primary;
1847 BUG_ON(mpic == NULL);
1849 printk(KERN_INFO "mpic: requesting IPIs...\n");
1852 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1853 mpic->ipi_vecs[0] + i);
1864 struct mpic *mpic = mpic_primary;
1867 BUG_ON(mpic == NULL);
1877 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1907 struct mpic *mpic = mpic_primary;
1913 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1915 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1916 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1920 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1921 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1925 if (mpic->flags & MPIC_FSL) {
1927 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1935 static void mpic_suspend_one(struct mpic *mpic)
1939 for (i = 0; i < mpic->num_sources; i++) {
1940 mpic->save_data[i].vecprio =
1942 mpic->save_data[i].dest =
1949 struct mpic *mpic = mpics;
1951 while (mpic) {
1952 mpic_suspend_one(mpic);
1953 mpic = mpic->next;
1959 static void mpic_resume_one(struct mpic *mpic)
1963 for (i = 0; i < mpic->num_sources; i++) {
1965 mpic->save_data[i].vecprio);
1967 mpic->save_data[i].dest);
1970 if (mpic->fixups) {
1971 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1975 if ((mpic->save_data[i].fixup_data & 1) == 0)
1981 writel(mpic->save_data[i].fixup_data & ~1,
1991 struct mpic *mpic = mpics;
1993 while (mpic) {
1994 mpic_resume_one(mpic);
1995 mpic = mpic->next;
2012 pr_err("mpic: Failed to register subsystem!\n");