Lines Matching defs:ipic
3 * arch/powerpc/sysdev/ipic.c
24 #include <asm/ipic.h>
26 #include "ipic.h"
28 static struct ipic * primary_ipic;
515 static inline struct ipic * ipic_from_irq(unsigned int virq)
522 struct ipic *ipic = ipic_from_irq(d->irq);
529 temp = ipic_read(ipic->regs, ipic_info[src].mask);
531 ipic_write(ipic->regs, ipic_info[src].mask, temp);
538 struct ipic *ipic = ipic_from_irq(d->irq);
545 temp = ipic_read(ipic->regs, ipic_info[src].mask);
547 ipic_write(ipic->regs, ipic_info[src].mask, temp);
558 struct ipic *ipic = ipic_from_irq(d->irq);
566 ipic_write(ipic->regs, ipic_info[src].ack, temp);
577 struct ipic *ipic = ipic_from_irq(d->irq);
584 temp = ipic_read(ipic->regs, ipic_info[src].mask);
586 ipic_write(ipic->regs, ipic_info[src].mask, temp);
589 ipic_write(ipic->regs, ipic_info[src].ack, temp);
600 struct ipic *ipic = ipic_from_irq(d->irq);
607 /* ipic supports only low assertion and high-to-low change senses
610 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
614 /* ipic supports only edge mode on external interrupts */
616 printk(KERN_ERR "ipic: edge sense not supported on internal "
631 /* only EXT IRQ senses are programmable on ipic
642 vold = ipic_read(ipic->regs, IPIC_SECNR);
649 ipic_write(ipic->regs, IPIC_SECNR, vnew);
674 /* Exact match, unless ipic node is NULL */
682 struct ipic *ipic = h->host_data;
684 irq_set_chip_data(virq, ipic);
699 struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
701 struct ipic *ipic;
709 ipic = kzalloc(sizeof(*ipic), GFP_KERNEL);
710 if (ipic == NULL)
713 ipic->irqhost = irq_domain_add_linear(node, NR_IPIC_INTS,
714 &ipic_host_ops, ipic);
715 if (ipic->irqhost == NULL) {
716 kfree(ipic);
720 ipic->regs = ioremap(res.start, resource_size(&res));
723 ipic_write(ipic->regs, IPIC_SICNR, 0x0);
740 ipic_write(ipic->regs, IPIC_SICFR, temp);
746 ipic_write(ipic->regs, IPIC_SERCR, temp);
749 temp = ipic_read(ipic->regs, IPIC_SEMSR);
756 ipic_write(ipic->regs, IPIC_SEMSR, temp);
758 primary_ipic = ipic;
761 ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
762 ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
767 return ipic;
821 struct ipic *ipic = primary_ipic;
823 ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
824 ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
825 ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
826 ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
827 ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
828 ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
829 ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
830 ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
831 ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
832 ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
833 ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
834 ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
841 ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
842 ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
843 ipic_write(ipic->regs, IPIC_SEMSR, 0);
844 ipic_write(ipic->regs, IPIC_SERMR, 0);
852 struct ipic *ipic = primary_ipic;
854 ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
855 ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
856 ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
857 ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
858 ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
859 ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
860 ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
861 ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
862 ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
863 ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
864 ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
865 ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
882 printk(KERN_DEBUG "Registering ipic system core operations\n");