Lines Matching refs:hose
66 static int fsl_pcie_check_link(struct pci_controller *hose)
70 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
71 if (hose->ops->read == fsl_indirect_read_config)
72 __indirect_read_config(hose, hose->first_busno, 0,
75 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
79 struct ccsr_pci __iomem *pci = hose->private_data;
93 struct pci_controller *hose = pci_bus_to_host(bus);
95 if (fsl_pcie_check_link(hose))
96 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
98 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
116 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
119 hose->dma_window_base_cur + hose->dma_window_size - 1;
122 static void setup_swiotlb_ops(struct pci_controller *hose)
125 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb;
128 static inline void setup_swiotlb_ops(struct pci_controller *hose) {}
193 static void setup_pci_atmu(struct pci_controller *hose)
195 struct ccsr_pci __iomem *pci = hose->private_data;
211 * hose->dma_window_size still get set.
215 if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) {
228 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
247 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
250 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
251 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
254 offset = hose->mem_offset[i];
255 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
259 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
265 if (hose->io_resource.flags & IORESOURCE_IO) {
271 (u64)hose->io_resource.start,
272 (u64)resource_size(&hose->io_resource),
273 (u64)hose->io_base_phys);
274 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
276 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
279 | (ilog2(hose->io_resource.end
280 - hose->io_resource.start + 1) - 1));
289 pr_err("%pOF: No outbound window space\n", hose->dn);
294 pr_err("%pOF: No space for inbound window\n", hose->dn);
299 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
300 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
308 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
312 pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar);
330 reg = of_get_property(hose->dn, "msi-address-64", &len);
335 pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn);
340 "unsupported\n", hose->dn, address);
348 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
354 "greater than memory size\n", hose->dn);
367 hose->dma_window_base_cur = 0x00000000;
368 hose->dma_window_size = (resource_size_t)sz;
401 pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn);
434 hose->dma_window_base_cur = 0x00000000;
435 hose->dma_window_size = (resource_size_t)paddr;
438 if (hose->dma_window_size < mem) {
444 hose->dn);
451 hose->dn);
453 pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn,
454 (u64)hose->dma_window_size);
458 static void __init setup_pci_cmd(struct pci_controller *hose)
463 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
466 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
468 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
473 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
475 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
481 struct pci_controller *hose = pci_bus_to_host(bus);
493 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
494 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
496 if (bus->parent == hose->bus && (is_pcie || no_link)) {
504 par = &hose->io_resource;
506 par = &hose->mem_resources[i-1];
519 struct pci_controller *hose;
551 hose = pcibios_alloc_controller(dev);
552 if (!hose)
556 hose->parent = &pdev->dev;
557 hose->first_busno = bus_range ? bus_range[0] : 0x0;
558 hose->last_busno = bus_range ? bus_range[1] : 0xff;
563 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
564 if (!hose->private_data)
567 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
571 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
573 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
575 hose->ops = &fsl_indirect_pcie_ops;
577 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
583 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
589 setup_pci_cmd(hose);
592 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
593 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
595 if (fsl_pcie_check_link(hose))
596 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
599 early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
602 early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
618 !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
619 early_read_config_word(hose, 0, 0,
622 early_write_config_word(hose, 0, 0,
629 (unsigned long long)rsrc.start, hose->first_busno,
630 hose->last_busno);
633 hose, hose->cfg_addr, hose->cfg_data);
637 pci_process_bridge_OF_ranges(hose, dev, is_primary);
640 setup_pci_atmu(hose);
643 setup_swiotlb_ops(hose);
648 iounmap(hose->private_data);
650 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
651 ((unsigned long)hose->cfg_addr & PAGE_MASK))
652 iounmap(hose->cfg_data);
653 iounmap(hose->cfg_addr);
654 pcibios_free_controller(hose);
688 struct pci_controller *hose = pci_bus_to_host(bus);
690 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
697 if (bus->number == hose->first_busno ||
698 bus->primary == hose->first_busno) {
704 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
714 struct pci_controller *hose = pci_bus_to_host(bus);
715 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
726 if (bus->number == hose->first_busno)
742 struct pci_controller *hose = pci_bus_to_host(bus);
745 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
757 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
783 WARN_ON(hose->dn->data);
784 hose->dn->data = pcie;
785 hose->ops = &mpc83xx_pcie_ops;
786 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
791 if (fsl_pcie_check_link(hose))
792 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
807 struct pci_controller *hose;
860 hose = pcibios_alloc_controller(dev);
861 if (!hose)
864 hose->first_busno = bus_range ? bus_range[0] : 0;
865 hose->last_busno = bus_range ? bus_range[1] : 0xff;
868 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
872 setup_indirect_pci(hose, rsrc_cfg.start,
878 (unsigned long long)rsrc_reg.start, hose->first_busno,
879 hose->last_busno);
882 hose, hose->cfg_addr, hose->cfg_data);
886 pci_process_bridge_OF_ranges(hose, dev, primary);
890 pcibios_free_controller(hose);
895 u64 fsl_pci_immrbar_base(struct pci_controller *hose)
899 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
923 pci_bus_read_config_dword(hose->bus,
1041 struct pci_controller *hose;
1045 list_for_each_entry(hose, &hose_list, list_node) {
1046 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
1050 res = &hose->mem_resources[i];
1152 struct pci_controller *hose = dev_id;
1153 struct ccsr_pci __iomem *pci = hose->private_data;
1165 static int fsl_pci_pme_probe(struct pci_controller *hose)
1173 /* Get hose's pci_dev */
1174 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
1181 pme_irq = irq_of_parse_and_map(hose->dn, 0);
1188 res = devm_request_irq(hose->parent, pme_irq,
1191 "[PCI] PME", hose);
1199 pci = hose->private_data;
1217 static void send_pme_turnoff_message(struct pci_controller *hose)
1219 struct ccsr_pci __iomem *pci = hose->private_data;
1238 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
1240 send_pme_turnoff_message(hose);
1245 struct pci_controller *hose, *tmp;
1247 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1248 fsl_pci_syscore_do_suspend(hose);
1253 static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
1255 struct ccsr_pci __iomem *pci = hose->private_data;
1273 setup_pci_atmu(hose);
1278 struct pci_controller *hose, *tmp;
1280 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1281 fsl_pci_syscore_do_resume(hose);