Lines Matching refs:val
275 u64 lpcr, val;
281 val = 0ULL;
282 val = SET_FIELD(VAS_XLATE_MSR_HV, val, 1);
283 val = SET_FIELD(VAS_XLATE_MSR_SF, val, 1);
285 val = SET_FIELD(VAS_XLATE_MSR_DR, val, 1);
286 val = SET_FIELD(VAS_XLATE_MSR_PR, val, 1);
288 write_hvwc_reg(window, VREG(XLATE_MSR), val);
291 val = 0ULL;
299 val = SET_FIELD(VAS_XLATE_LPCR_PAGE_SIZE, val, 5);
300 val = SET_FIELD(VAS_XLATE_LPCR_ISL, val, lpcr & LPCR_ISL);
301 val = SET_FIELD(VAS_XLATE_LPCR_TC, val, lpcr & LPCR_TC);
302 val = SET_FIELD(VAS_XLATE_LPCR_SC, val, 0);
303 write_hvwc_reg(window, VREG(XLATE_LPCR), val);
312 val = 0ULL;
313 val = SET_FIELD(VAS_XLATE_MODE, val, radix_enabled() ? 3 : 2);
314 write_hvwc_reg(window, VREG(XLATE_CTL), val);
319 val = 0ULL;
320 val = SET_FIELD(VAS_AMR, val, mfspr(SPRN_AMR));
321 write_hvwc_reg(window, VREG(AMR), val);
323 val = 0ULL;
324 val = SET_FIELD(VAS_SEIDR, val, 0);
325 write_hvwc_reg(window, VREG(SEIDR), val);
363 u64 val;
368 val = 0ULL;
369 val = SET_FIELD(VAS_LPID, val, winctx->lpid);
370 write_hvwc_reg(window, VREG(LPID), val);
372 val = 0ULL;
373 val = SET_FIELD(VAS_PID_ID, val, winctx->pidr);
374 write_hvwc_reg(window, VREG(PID), val);
378 val = 0ULL;
379 val = SET_FIELD(VAS_FAULT_TX_WIN, val, winctx->fault_win_id);
380 write_hvwc_reg(window, VREG(FAULT_TX_WIN), val);
385 val = 0ULL;
386 val = SET_FIELD(VAS_HV_INTR_SRC_RA, val, winctx->irq_port);
387 write_hvwc_reg(window, VREG(HV_INTR_SRC_RA), val);
389 val = 0ULL;
390 val = SET_FIELD(VAS_PSWID_EA_HANDLE, val, winctx->pswid);
391 write_hvwc_reg(window, VREG(PSWID), val);
406 val = winctx->rx_fifo;
407 val = SET_FIELD(VAS_PAGE_MIGRATION_SELECT, val, 0);
408 write_hvwc_reg(window, VREG(LFIFO_BAR), val);
410 val = 0ULL;
411 val = SET_FIELD(VAS_LDATA_STAMP, val, winctx->data_stamp);
412 write_hvwc_reg(window, VREG(LDATA_STAMP_CTL), val);
414 val = 0ULL;
415 val = SET_FIELD(VAS_LDMA_TYPE, val, winctx->dma_type);
416 val = SET_FIELD(VAS_LDMA_FIFO_DISABLE, val, winctx->fifo_disable);
417 write_hvwc_reg(window, VREG(LDMA_CACHE_CTL), val);
423 val = 0ULL;
424 val = SET_FIELD(VAS_LRX_WCRED, val, winctx->wcreds_max);
425 write_hvwc_reg(window, VREG(LRX_WCRED), val);
427 val = 0ULL;
428 val = SET_FIELD(VAS_TX_WCRED, val, winctx->wcreds_max);
429 write_hvwc_reg(window, VREG(TX_WCRED), val);
436 val = 0ULL;
437 val = SET_FIELD(VAS_LFIFO_SIZE, val, ilog2(fifo_size));
438 write_hvwc_reg(window, VREG(LFIFO_SIZE), val);
450 val = 0ULL;
451 val = SET_FIELD(VAS_LRX_WIN_ID, val, winctx->rx_win_id);
452 write_hvwc_reg(window, VREG(LRFIFO_WIN_PTR), val);
456 val = 0ULL;
457 val = SET_FIELD(VAS_NOTIFY_DISABLE, val, winctx->notify_disable);
458 val = SET_FIELD(VAS_INTR_DISABLE, val, winctx->intr_disable);
459 val = SET_FIELD(VAS_NOTIFY_EARLY, val, winctx->notify_early);
460 val = SET_FIELD(VAS_NOTIFY_OSU_INTR, val, winctx->notify_os_intr_reg);
461 write_hvwc_reg(window, VREG(LNOTIFY_CTL), val);
463 val = 0ULL;
464 val = SET_FIELD(VAS_LNOTIFY_PID, val, winctx->lnotify_pid);
465 write_hvwc_reg(window, VREG(LNOTIFY_PID), val);
467 val = 0ULL;
468 val = SET_FIELD(VAS_LNOTIFY_LPID, val, winctx->lnotify_lpid);
469 write_hvwc_reg(window, VREG(LNOTIFY_LPID), val);
471 val = 0ULL;
472 val = SET_FIELD(VAS_LNOTIFY_TID, val, winctx->lnotify_tid);
473 write_hvwc_reg(window, VREG(LNOTIFY_TID), val);
475 val = 0ULL;
476 val = SET_FIELD(VAS_LNOTIFY_MIN_SCOPE, val, winctx->min_scope);
477 val = SET_FIELD(VAS_LNOTIFY_MAX_SCOPE, val, winctx->max_scope);
478 write_hvwc_reg(window, VREG(LNOTIFY_SCOPE), val);
487 val = 0ULL;
488 val = SET_FIELD(VAS_PUSH_TO_MEM, val, 1);
489 write_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), val);
492 val = 0ULL;
493 val = SET_FIELD(VAS_WINCTL_REJ_NO_CREDIT, val, winctx->rej_no_credit);
494 val = SET_FIELD(VAS_WINCTL_PIN, val, winctx->pin_win);
495 val = SET_FIELD(VAS_WINCTL_TX_WCRED_MODE, val, winctx->tx_wcred_mode);
496 val = SET_FIELD(VAS_WINCTL_RX_WCRED_MODE, val, winctx->rx_wcred_mode);
497 val = SET_FIELD(VAS_WINCTL_TX_WORD_MODE, val, winctx->tx_word_mode);
498 val = SET_FIELD(VAS_WINCTL_RX_WORD_MODE, val, winctx->rx_word_mode);
499 val = SET_FIELD(VAS_WINCTL_FAULT_WIN, val, winctx->fault_win);
500 val = SET_FIELD(VAS_WINCTL_NX_WIN, val, winctx->nx_win);
501 val = SET_FIELD(VAS_WINCTL_OPEN, val, 1);
502 write_hvwc_reg(window, VREG(WINCTL), val);
1139 uint64_t val;
1156 val = SET_FIELD(RMA_LSMP_REPORT_ENABLE, 0ULL, 1);
1157 addr += val;
1192 u64 val;
1196 val = read_hvwc_reg(window, VREG(WINCTL));
1198 mode = GET_FIELD(VAS_WINCTL_TX_WCRED_MODE, val);
1200 mode = GET_FIELD(VAS_WINCTL_RX_WCRED_MODE, val);
1206 val = read_hvwc_reg(window, VREG(TX_WCRED));
1207 creds = GET_FIELD(VAS_TX_WCRED, val);
1209 val = read_hvwc_reg(window, VREG(LRX_WCRED));
1210 creds = GET_FIELD(VAS_LRX_WCRED, val);
1221 val = 0;
1246 u64 val;
1250 val = read_hvwc_reg(window, VREG(WIN_STATUS));
1251 busy = GET_FIELD(VAS_WIN_BUSY, val);
1253 val = 0;
1296 u64 val;
1298 val = read_hvwc_reg(window, VREG(WINCTL));
1299 val = SET_FIELD(VAS_WINCTL_PIN, val, 0);
1300 val = SET_FIELD(VAS_WINCTL_OPEN, val, 0);
1301 write_hvwc_reg(window, VREG(WINCTL), val);
1383 uint64_t val;
1385 val = 0ULL;
1387 val = SET_FIELD(VAS_TX_WCRED, val, 1);
1388 write_hvwc_reg(window, VREG(TX_WCRED_ADDER), val);
1390 val = SET_FIELD(VAS_LRX_WCRED, val, 1);
1391 write_hvwc_reg(window, VREG(LRX_WCRED_ADDER), val);