Lines Matching refs:pdev

146 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
148 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
158 pdev->dev.archdata.iov_data = iov;
162 res = &pdev->resource[i + PCI_IOV_RESOURCES];
166 dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n",
171 vf_bar_sz = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
192 pci_err(pdev, "VF BAR%d: %pR can't be mapped in single PE mode\n",
205 pci_dbg(pdev, " Fixing VF BAR%d: %pR to\n", i, res);
207 pci_dbg(pdev, " %pR\n", res);
209 pci_info(pdev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
220 res = &pdev->resource[i + PCI_IOV_RESOURCES];
225 pdev->dev.archdata.iov_data = NULL;
229 void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
231 if (WARN_ON(pci_dev_is_added(pdev)))
234 if (pdev->is_virtfn) {
235 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);
238 * VF PEs are single-device PEs so their pdev pointer needs to
239 * be set. The pdev doesn't exist when the PE is allocated (in
242 pe->pdev = pdev;
244 } else if (pdev->is_physfn) {
249 pnv_pci_ioda_fixup_iov_resources(pdev);
253 resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
256 resource_size_t align = pci_iov_resource_size(pdev, resno);
257 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
258 struct pnv_iov_data *iov = pnv_iov_get(pdev);
290 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
296 phb = pci_bus_to_pnvhb(pdev->bus);
297 iov = pnv_iov_get(pdev);
421 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
432 phb = pci_bus_to_pnvhb(pdev->bus);
433 iov = pnv_iov_get(pdev);
436 res = &pdev->resource[i + PCI_IOV_RESOURCES];
457 size = pci_iov_resource_size(pdev, PCI_IOV_RESOURCES + i);
477 pnv_pci_vf_release_m64(pdev, num_vfs);
481 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
486 phb = pci_bus_to_pnvhb(pdev->bus);
488 if (!pdev->is_physfn)
493 if (pe->parent_dev != pdev)
597 static void pnv_pci_sriov_disable(struct pci_dev *pdev)
602 iov = pnv_iov_get(pdev);
610 pnv_ioda_release_vf_PE(pdev);
614 pnv_pci_vf_resource_shift(pdev, -base_pe);
617 pnv_pci_vf_release_m64(pdev, num_vfs);
620 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
629 if (!pdev->is_physfn)
632 phb = pci_bus_to_pnvhb(pdev->bus);
633 pdn = pci_get_pdn(pdev);
634 iov = pnv_iov_get(pdev);
638 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
639 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
646 pe->parent_dev = pdev;
652 pci_domain_nr(pdev->bus), pdev->bus->number,
658 pe->pdev = NULL;
680 static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
688 phb = pci_bus_to_pnvhb(pdev->bus);
689 iov = pnv_iov_get(pdev);
699 pci_err(pdev, "SR-IOV is not supported on this PHB\n");
704 dev_info(&pdev->dev, "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n");
711 pci_err(pdev, "Unable to allocate PEs for %d VFs\n", num_vfs);
719 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
721 dev_info(&pdev->dev, "Not enough M64 window resources\n");
731 ret = pnv_pci_vf_resource_shift(pdev, base_pe->pe_number);
737 pnv_ioda_setup_vf_PE(pdev, num_vfs);
742 pnv_pci_vf_release_m64(pdev, num_vfs);
751 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
753 pnv_pci_sriov_disable(pdev);
756 remove_sriov_vf_pdns(pdev);
760 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
763 add_sriov_vf_pdns(pdev);
765 return pnv_pci_sriov_enable(pdev, num_vfs);