Lines Matching refs:iov
152 struct pnv_iov_data *iov;
155 iov = kzalloc(sizeof(*iov), GFP_KERNEL);
156 if (!iov)
158 pdev->dev.archdata.iov_data = iov;
197 iov->m64_single_mode[i] = true;
212 iov->need_shift = true;
226 kfree(iov);
258 struct pnv_iov_data *iov = pnv_iov_get(pdev);
261 * iov can be null if we have an SR-IOV device with IOV BAR that can't
266 if (!iov)
274 if (iov->m64_single_mode[resno - PCI_IOV_RESOURCES])
292 struct pnv_iov_data *iov;
297 iov = pnv_iov_get(pdev);
299 for_each_set_bit(window_id, iov->used_m64_bar_mask, MAX_M64_BARS) {
404 static int pnv_pci_alloc_m64_bar(struct pnv_phb *phb, struct pnv_iov_data *iov)
416 set_bit(win, iov->used_m64_bar_mask);
423 struct pnv_iov_data *iov;
433 iov = pnv_iov_get(pdev);
441 if (!iov->m64_single_mode[i]) {
442 win = pnv_pci_alloc_m64_bar(phb, iov);
458 base_pe_num = iov->vf_pe_arr[0].pe_number;
461 win = pnv_pci_alloc_m64_bar(phb, iov);
512 struct pnv_iov_data *iov;
519 iov = pnv_iov_get(dev);
529 num_vfs = iov->num_vfs;
534 if (iov->m64_single_mode[i])
567 if (iov->m64_single_mode[i])
579 devm_release_resource(&dev->dev, &iov->holes[i]);
580 memset(&iov->holes[i], 0, sizeof(iov->holes[i]));
586 iov->holes[i].start = res2.start;
587 iov->holes[i].end = res2.start + size * offset - 1;
588 iov->holes[i].flags = IORESOURCE_BUS;
589 iov->holes[i].name = "pnv_iov_reserved";
591 &iov->holes[i]);
600 struct pnv_iov_data *iov;
602 iov = pnv_iov_get(pdev);
603 if (WARN_ON(!iov))
606 num_vfs = iov->num_vfs;
607 base_pe = iov->vf_pe_arr[0].pe_number;
613 if (iov->need_shift)
626 struct pnv_iov_data *iov;
634 iov = pnv_iov_get(pdev);
642 pe = &iov->vf_pe_arr[vf_index];
683 struct pnv_iov_data *iov;
689 iov = pnv_iov_get(pdev);
703 if (!iov) {
715 iov->vf_pe_arr = base_pe;
716 iov->num_vfs = num_vfs;
730 if (iov->need_shift) {
746 pnv_ioda_free_pe(&iov->vf_pe_arr[i]);