Lines Matching defs:edev

267 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
271 	if (!edev || !edev->pcie_cap)
326 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
338 	if (!edev || edev->pe)
342 	if (edev->pdev) {
343 		pr_debug("%s: found existing edev for %04x:%02x:%02x.%01x\n",
346 		return edev;
353 	eeh_edev_dbg(edev, "Probing device\n");
356 	edev->mode	&= 0xFFFFFF00;
357 	edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
358 	edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
359 	edev->af_cap   = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF);
360 	edev->aer_cap  = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
362 		edev->mode |= EEH_DEV_BRIDGE;
363 		if (edev->pcie_cap) {
364 			pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
368 				edev->mode |= EEH_DEV_ROOT_PORT;
370 				edev->mode |= EEH_DEV_DS_PORT;
374 	edev->pe_config_addr = phb->ioda.pe_rmap[config_addr];
379 	ret = eeh_pe_tree_insert(edev, upstream_pe);
381 		eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n", ret);
411 		edev->pe->state |= EEH_PE_CFG_RESTRICTED;
419 	if (!(edev->pe->state & EEH_PE_PRI_BUS)) {
420 		edev->pe->bus = pci_find_bus(hose->global_number,
422 		if (edev->pe->bus)
423 			edev->pe->state |= EEH_PE_PRI_BUS;
437 	eeh_save_bars(edev);
439 	eeh_edev_dbg(edev, "EEH enabled on device\n");
441 	return edev;
804 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
805 	int aer = edev ? edev->aer_cap : 0;
817 			eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,
820 			eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,
824 		eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);
826 		eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);
831 		eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);
833 		eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);
839 			eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,
842 			eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,
911 	struct eeh_dev *edev = pdn->edev;
916 		eeh_ops->read_config(edev, pos, 2, &status);
931 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
934 	if (WARN_ON(!edev->pcie_cap))
937 	eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, &reg);
945 					 edev->pcie_cap + PCI_EXP_DEVSTA,
947 		eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
950 		eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
955 		eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
958 		eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
969 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
972 	if (WARN_ON(!edev->af_cap))
975 	eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap);
988 					 edev->af_cap + PCI_AF_CTRL,
990 		eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL,
995 		eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0);
1005 	struct eeh_dev *edev;
1010 	edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);
1011 	pdn = eeh_dev_to_pdn(edev);
1210 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1212 	if (!edev || !edev->pe)
1220 	if (edev->physfn && (edev->pe->state & EEH_PE_RESET))
1223 	if (edev->pe->state & EEH_PE_CFG_BLOCKED)
1229 static int pnv_eeh_read_config(struct eeh_dev *edev,
1232 	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
1245 static int pnv_eeh_write_config(struct eeh_dev *edev,
1248 	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
1603 static int pnv_eeh_restore_config(struct eeh_dev *edev)
1608 	if (!edev)
1611 	if (edev->physfn)
1614 	phb = edev->controller->private_data;
1616 			      OPAL_REINIT_PCI_DEV, edev->bdfn);
1620 			__func__, edev->bdfn, ret);