Lines Matching refs:hose
69 /* Lookup the "bus-range" property for the hose */
96 static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,
101 if (bus == hose->first_busno) {
110 out_le32(hose->cfg_addr, caddr);
111 } while (in_le32(hose->cfg_addr) != caddr);
114 return hose->cfg_data + offset;
120 struct pci_controller *hose;
123 hose = pci_bus_to_host(bus);
124 if (hose == NULL)
127 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
151 struct pci_controller *hose;
154 hose = pci_bus_to_host(bus);
155 if (hose == NULL)
158 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
195 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
198 if (bus == hose->first_busno) {
201 return hose->cfg_data + u3_ht_cfa0(devfn, offset);
203 return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
206 static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,
211 addr = hose->cfg_addr;
229 static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,
234 addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));
257 struct pci_controller *hose;
260 hose = pci_bus_to_host(bus);
261 if (hose == NULL)
264 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
265 return u3_ht_root_read_config(hose, offset, len, val);
270 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
295 struct pci_controller *hose;
298 hose = pci_bus_to_host(bus);
299 if (hose == NULL)
302 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
303 return u3_ht_root_write_config(hose, offset, len, val);
308 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
352 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
357 if (bus == hose->first_busno)
364 out_le32(hose->cfg_addr, caddr);
365 } while (in_le32(hose->cfg_addr) != caddr);
368 return hose->cfg_data + offset;
374 struct pci_controller *hose;
377 hose = pci_bus_to_host(bus);
378 if (hose == NULL)
382 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
405 struct pci_controller *hose;
408 hose = pci_bus_to_host(bus);
409 if (hose == NULL)
413 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
440 static void __init setup_u3_agp(struct pci_controller* hose)
451 hose->first_busno = 0xf0;
452 hose->last_busno = 0xff;
453 hose->ops = &u3_agp_pci_ops;
454 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
455 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
457 u3_agp = hose;
460 static void __init setup_u4_pcie(struct pci_controller* hose)
465 hose->ops = &u4_pcie_pci_ops;
466 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
467 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
469 u4_pcie = hose;
472 static void __init setup_u3_ht(struct pci_controller* hose)
474 hose->ops = &u3_ht_pci_ops;
480 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
481 hose->cfg_addr = ioremap(0xf8070000, 0x1000);
483 hose->first_busno = 0;
484 hose->last_busno = 0xef;
486 u3_ht = hose;
492 struct pci_controller *hose;
505 hose = pcibios_alloc_controller(dev);
506 if (hose == NULL)
508 hose->first_busno = bus_range ? bus_range[0] : 0;
509 hose->last_busno = bus_range ? bus_range[1] : 0xff;
510 hose->controller_ops = maple_pci_controller_ops;
514 setup_u3_agp(hose);
518 setup_u3_ht(hose);
522 setup_u4_pcie(hose);
527 disp_name, hose->first_busno, hose->last_busno);
531 pci_process_bridge_OF_ranges(hose, dev, primary);
537 isa_bridge_find_early(hose);
570 struct pci_controller *hose = pci_bus_to_host(bridge->bus);
573 if (hose != u3_agp)
580 np = hose->dn;