Lines Matching refs:val
42 #define READ_SHADOW_REG(val, reg) \
46 (val) = shadow_regs->reg; \
49 #define READ_MMIO_UPPER32(val, reg) \
53 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
63 u32 val_in_latch, val = 0;
70 READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
72 READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
76 return val;
80 void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
90 WRITE_WO_MMIO(pm_ctr[phys_ctr], val);
115 u32 val;
118 val = cbe_read_phys_ctr(cpu, phys_ctr);
121 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
123 return val;
127 void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
138 val = (val << 16) | (phys_val & 0xffff);
140 val = (val & 0xffff) | (phys_val & 0xffff0000);
143 cbe_write_phys_ctr(cpu, phys_ctr, val);
163 void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
166 WRITE_WO_MMIO(pm07_control[ctr], val);
176 u32 val = 0;
180 READ_SHADOW_REG(val, group_control);
184 READ_SHADOW_REG(val, debug_bus_control);
188 READ_MMIO_UPPER32(val, trace_address);
192 READ_SHADOW_REG(val, ext_tr_timer);
196 READ_MMIO_UPPER32(val, pm_status);
200 READ_SHADOW_REG(val, pm_control);
204 READ_MMIO_UPPER32(val, pm_interval);
208 READ_SHADOW_REG(val, pm_start_stop);
212 return val;
216 void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
220 WRITE_WO_MMIO(group_control, val);
224 WRITE_WO_MMIO(debug_bus_control, val);
228 WRITE_WO_MMIO(trace_address, val);
232 WRITE_WO_MMIO(ext_tr_timer, val);
236 WRITE_WO_MMIO(pm_status, val);
240 WRITE_WO_MMIO(pm_control, val);
244 WRITE_WO_MMIO(pm_interval, val);
248 WRITE_WO_MMIO(pm_start_stop, val);