Lines Matching refs:port

657 	int (*port_init_hw)(struct ppc4xx_pciex_port *port);
658 int (*setup_utl)(struct ppc4xx_pciex_port *port);
659 void (*check_link)(struct ppc4xx_pciex_port *port);
664 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
673 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
676 port->index, sdr_offset, timeout_ms, val);
684 static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
687 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
689 port->index);
696 static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
698 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
707 if (!port->has_ibpre ||
708 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
712 port->index);
713 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
716 "PCIE%d: Link up failed\n", port->index);
719 "PCIE%d: link is up !\n", port->index);
720 port->link = 1;
723 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
843 static int __init ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
847 if (port->endpoint)
852 if (port->index == 0)
857 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
858 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
860 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
861 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
863 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
865 if (port->index == 0) {
866 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
868 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
870 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
872 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
875 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
878 return ppc4xx_pciex_port_reset_sdr(port);
881 static int __init ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
883 return ppc440spe_pciex_init_port_hw(port);
886 static int __init ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
888 int rc = ppc440spe_pciex_init_port_hw(port);
890 port->has_ibpre = 1;
895 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
898 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
903 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
904 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
905 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
906 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
907 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
908 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
909 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
910 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
915 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
918 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
947 static int __init ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
952 if (port->endpoint)
957 if (port->index == 0) {
965 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
966 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
967 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
969 switch (port->index) {
996 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
997 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
1002 switch (port->index) {
1013 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1014 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1018 port->has_ibpre = 1;
1020 return ppc4xx_pciex_port_reset_sdr(port);
1023 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1025 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1030 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
1031 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
1032 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1033 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1034 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
1035 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1036 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1037 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
1038 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1054 /* Return the number of pcie port */
1058 static int __init apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1067 * PT quad port, SAS LSI 1064E)
1073 if (port->endpoint)
1080 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
1081 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1082 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1092 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1093 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
1097 val = PESDR0_460EX_RSTSTA - port->sdr_base;
1098 if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) {
1102 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1103 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1107 port->has_ibpre = 1;
1193 * third PCIe port
1206 static int __init ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1209 if (port->endpoint)
1210 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1213 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1216 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
1220 port->has_ibpre = 1;
1222 return ppc4xx_pciex_port_reset_sdr(port);
1225 static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
1228 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
1230 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000);
1234 static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port *port)
1239 port->link = 0;
1241 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1244 port->node);
1254 port->link = 1;
1276 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
1279 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
1283 if (port->endpoint)
1284 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
1286 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
1290 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
1294 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
1297 static int __init ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1301 if (port->endpoint)
1306 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
1309 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1310 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1311 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
1312 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
1321 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
1323 ppc405ex_pcie_phy_reset(port);
1325 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
1327 port->has_ibpre = 1;
1329 return ppc4xx_pciex_port_reset_sdr(port);
1332 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1334 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1339 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
1340 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1341 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1342 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
1343 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1344 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1345 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
1346 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1348 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
1370 static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port)
1374 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000,
1377 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
1381 port->index);
1394 printk(KERN_INFO "PCIE%d: link is up !\n", port->index);
1395 port->link = 1;
1397 printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index);
1461 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1464 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1465 RES_TO_U32_HIGH(port->cfg_space.start));
1466 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1467 RES_TO_U32_LOW(port->cfg_space.start));
1470 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1473 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1474 RES_TO_U32_HIGH(port->utl_regs.start));
1475 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1476 RES_TO_U32_LOW(port->utl_regs.start));
1479 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1482 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1483 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1484 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1485 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1488 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1494 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1502 ppc4xx_pciex_port_init_mapping(port);
1505 ppc4xx_pciex_hwops->check_link(port);
1510 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1511 BUG_ON(port->utl_base == NULL);
1517 ppc4xx_pciex_hwops->setup_utl(port);
1522 if (port->sdr_base) {
1523 if (of_device_is_compatible(port->node,
1525 if (port->link && ppc4xx_pciex_wait_on_sdr(port,
1529 port->index);
1530 port->link = 0;
1532 } else if (port->link &&
1533 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1536 port->index);
1537 port->link = 0;
1540 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1548 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1555 if (port->endpoint && bus->number != port->hose->first_busno)
1559 if (bus->number > port->hose->last_busno) {
1569 if (bus->number == port->hose->first_busno && devfn != 0)
1573 if (bus->number == (port->hose->first_busno + 1) &&
1578 if ((bus->number != port->hose->first_busno) && !port->link)
1584 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1593 if (bus->number == port->hose->first_busno)
1594 return (void __iomem *)port->hose->cfg_addr;
1596 relbus = bus->number - (port->hose->first_busno + 1);
1597 return (void __iomem *)port->hose->cfg_data +
1605 struct ppc4xx_pciex_port *port =
1610 BUG_ON(hose != port->hose);
1612 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1615 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1622 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1623 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1626 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1646 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1653 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1662 struct ppc4xx_pciex_port *port =
1667 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1670 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1677 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1678 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1697 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1708 static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
1739 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1740 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1741 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1743 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
1744 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1748 port->node, "ibm,plb-pciex-476fpe") ||
1750 port->node, "ibm,plb-pciex-476gtr"))
1751 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1755 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1762 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1763 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1764 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1765 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL,
1771 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1772 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1773 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1775 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL,
1784 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1800 port->node);
1805 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1823 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1833 ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1838 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1846 if (port->endpoint) {
1879 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
1881 port->node, "ibm,plb-pciex-476fpe") ||
1883 port->node, "ibm,plb-pciex-476gtr"))
1912 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1923 if (of_get_property(port->node, "primary", NULL))
1927 bus_range = of_get_property(port->node, "bus-range", NULL);
1930 hose = pcibios_alloc_controller(port->node);
1934 /* We stick the port number in "indirect_type" so the config space
1935 * ops can retrieve the port data structure easily
1937 hose->indirect_type = port->index;
1954 if (!port->endpoint) {
1958 cfg_data = ioremap(port->cfg_space.start +
1963 port->node);
1972 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1975 port->node);
1980 pr_debug("PCIE %pOF, bus %d..%d\n", port->node,
1987 port->hose = hose;
1990 if (!port->endpoint) {
1992 * Set bus numbers on our root port
2005 pci_process_bridge_OF_ranges(hose, port->node, primary);
2012 ppc4xx_configure_pciex_POMs(port, hose, mbase);
2015 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
2025 pval = of_get_property(port->node, "vendor-id", NULL);
2029 if (!port->endpoint)
2030 val = 0xaaa0 + port->index;
2032 val = 0xeee0 + port->index;
2036 pval = of_get_property(port->node, "device-id", NULL);
2040 if (!port->endpoint)
2041 val = 0xbed0 + port->index;
2043 val = 0xfed0 + port->index;
2048 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
2051 if (!port->endpoint) {
2056 port->index);
2062 port->index);
2077 struct ppc4xx_pciex_port *port;
2088 /* Get the port number from the device-tree */
2089 pval = of_get_property(np, "port", NULL);
2091 printk(KERN_ERR "PCIE: Can't find port number for %pOF\n", np);
2096 printk(KERN_ERR "PCIE: port number out of range for %pOF\n",
2100 port = &ppc4xx_pciex_ports[portno];
2101 port->index = portno;
2107 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
2111 port->node = of_node_get(np);
2119 port->sdr_base = *pval;
2123 * Resulting from this setup this PCIe port will be configured
2126 if (of_node_is_type(port->node, "pci-endpoint")) {
2127 port->endpoint = 1;
2128 } else if (of_node_is_type(port->node, "pci")) {
2129 port->endpoint = 0;
2137 if (of_address_to_resource(np, 0, &port->cfg_space)) {
2142 if (of_address_to_resource(np, 1, &port->utl_regs)) {
2153 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
2155 /* Initialize the port specific registers */
2156 if (ppc4xx_pciex_port_init(port)) {
2157 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
2162 ppc4xx_pciex_port_setup_hose(port);