Lines Matching defs:cache
163 unsigned int cache;
165 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK;
166 return cache;
261 unsigned int unit, pmc, cache, ebb;
272 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
275 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
329 } else if (cache & 0x7) {
331 * L2/L3 events contain a cache selector field, which is
336 * have a cache selector of zero. The bank selector (bit 3) is
344 value |= CNST_L1_QUAL_VAL(cache);
417 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
466 cache = dc_ic_rld_quad_l1_sel(event[i]);
467 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
470 cache = dc_ic_rld_quad_l1_sel(event[i]);
471 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;