Lines Matching refs:ctr
282 static void set_pm_event(u32 ctr, int event, u32 unit_mask)
291 pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES;
292 p = &(pm_signal[ctr]);
299 pm_regs.pm07_cntrl[ctr] = 0;
309 p = &(pm_signal[ctr]);
315 pm_regs.pm07_cntrl[ctr] = 0;
316 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);
317 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);
318 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);
343 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit);
345 pm_regs.pm07_cntrl[ctr] = 0;
424 static inline void enable_ctr(u32 cpu, u32 ctr, u32 *pm07_cntrl)
427 pm07_cntrl[ctr] |= CBE_PM_CTR_ENABLE;
428 cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]);
559 static int cell_reg_setup_spu_cycles(struct op_counter_config *ctr,
562 spu_cycle_reset = ctr[0].count;
681 static int cell_reg_setup_spu_events(struct op_counter_config *ctr,
736 set_pm_event(0, ctr[0].event, ctr[0].unit_mask);
738 reset_value[0] = 0xFFFFFFFF - ctr[0].count;
750 static int cell_reg_setup_ppu(struct op_counter_config *ctr,
771 pmc_cntrl[0][i].evnts = ctr[i].event;
772 pmc_cntrl[0][i].masks = ctr[i].unit_mask;
773 pmc_cntrl[0][i].enabled = ctr[i].enabled;
785 if ((ctr[i].event >= 2100) && (ctr[i].event <= 2111))
786 pmc_cntrl[1][i].evnts = ctr[i].event + 19;
787 else if (ctr[i].event == 2203)
788 pmc_cntrl[1][i].evnts = ctr[i].event;
789 else if ((ctr[i].event >= 2200) && (ctr[i].event <= 2215))
790 pmc_cntrl[1][i].evnts = ctr[i].event + 16;
792 pmc_cntrl[1][i].evnts = ctr[i].event;
794 pmc_cntrl[1][i].masks = ctr[i].unit_mask;
795 pmc_cntrl[1][i].enabled = ctr[i].enabled;
813 reset_value[i] = 0xFFFFFFFF - ctr[i].count;
834 static int cell_reg_setup(struct op_counter_config *ctr,
866 if (ctr[0].event == SPU_CYCLES_EVENT_NUM) {
868 ret = cell_reg_setup_spu_cycles(ctr, sys, num_ctrs);
869 } else if ((ctr[0].event >= SPU_EVENT_NUM_START) &&
870 (ctr[0].event <= SPU_EVENT_NUM_STOP)) {
872 spu_cycle_reset = ctr[0].count;
880 cell_reg_setup_spu_events(ctr, sys, num_ctrs);
883 ret = cell_reg_setup_ppu(ctr, sys, num_ctrs);
1241 static int cell_global_start_spu_cycles(struct op_counter_config *ctr)
1331 static int cell_global_start_spu_events(struct op_counter_config *ctr)
1394 static int cell_global_start_ppu(struct op_counter_config *ctr)
1440 static int cell_global_start(struct op_counter_config *ctr)
1443 return cell_global_start_spu_cycles(ctr);
1445 return cell_global_start_spu_events(ctr);
1447 return cell_global_start_ppu(ctr);
1479 struct op_counter_config *ctr)
1513 && ctr[0].enabled)
1597 struct op_counter_config *ctr)
1638 && ctr[i].enabled) {
1670 struct op_counter_config *ctr)
1673 cell_handle_interrupt_ppu(regs, ctr);
1675 cell_handle_interrupt_spu(regs, ctr);