Lines Matching refs:op
86 struct instruction_op *op)
93 op->type |= DECCTR;
501 static int do_fp_load(struct instruction_op *op, unsigned long ea,
514 nb = GETSIZE(op->type);
519 rn = op->reg;
530 if (op->type & FPCONV)
532 else if (op->type & SIGNEXT)
554 static int do_fp_store(struct instruction_op *op, unsigned long ea,
566 nb = GETSIZE(op->type);
571 rn = op->reg;
578 if (op->type & FPCONV)
709 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
718 size = GETSIZE(op->type);
721 switch (op->element_size) {
727 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
740 if (op->type & SIGNEXT) {
743 } else if (op->vsx_flags & VSX_FPCONV) {
753 } else if (op->vsx_flags & VSX_SPLAT)
764 if (op->vsx_flags & VSX_SPLAT) {
793 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
803 size = GETSIZE(op->type);
805 switch (op->element_size) {
810 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
824 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
869 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
873 int reg = op->reg;
876 int size = GETSIZE(op->type);
881 emulate_vsx_load(op, &buf, mem, cross_endian);
901 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
905 int reg = op->reg;
908 int size = GETSIZE(op->type);
929 emulate_vsx_store(op, &buf, mem, cross_endian);
960 #define __put_user_asmx(x, addr, err, op, cr) \
964 "1: " op " %2,0,%3\n" \
976 #define __get_user_asmx(x, addr, err, op) \
980 "1: "op" %1,0,%2\n" \
991 #define __cacheop_user_asmx(addr, err, op) \
993 "1: "op" 0,%1\n" \
1004 struct instruction_op *op)
1006 long val = op->val;
1008 op->type |= SETCC;
1009 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
1015 op->ccval |= 0x80000000;
1017 op->ccval |= 0x40000000;
1019 op->ccval |= 0x20000000;
1022 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1026 op->xerval |= XER_CA32;
1028 op->xerval &= ~XER_CA32;
1033 struct instruction_op *op, int rd,
1041 op->type = COMPUTE + SETREG + SETXER;
1042 op->reg = rd;
1043 op->val = val;
1050 op->xerval = regs->xer;
1052 op->xerval |= XER_CA;
1054 op->xerval &= ~XER_CA;
1056 set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1061 struct instruction_op *op,
1066 op->type = COMPUTE + SETCC;
1075 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1079 struct instruction_op *op,
1085 op->type = COMPUTE + SETCC;
1094 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1098 struct instruction_op *op,
1110 op->val = out_val;
1118 struct instruction_op *op,
1129 op->val = out;
1135 op->val = out & 0x0000003f0000003fULL;
1140 op->val = out; /* popcntd */
1145 struct instruction_op *op,
1158 op->val = perm;
1166 struct instruction_op *op,
1173 op->val = res & 0x0000000100000001ULL;
1178 op->val = res & 1; /*prtyd */
1214 * Decode an instruction, and return information about it in *op
1217 * instructions can be emulated just using the information in *op.
1220 * updating *regs with the information in *op, -1 if we need the
1224 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1240 op->type = COMPUTE;
1245 op->type = BRANCH;
1249 op->val = truncate_if_32bit(regs->msr, imm);
1251 op->type |= SETLK;
1252 if (branch_taken(word, regs, op))
1253 op->type |= BRTAKEN;
1258 op->type = SYSCALL;
1261 op->type = SYSCALL_VECTORED_0;
1265 op->type = UNKNOWN;
1269 op->type = BRANCH | BRTAKEN;
1275 op->val = truncate_if_32bit(regs->msr, imm);
1277 op->type |= SETLK;
1282 op->type = COMPUTE + SETCC;
1288 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1293 op->type = BRANCH;
1295 op->val = truncate_if_32bit(regs->msr, imm);
1297 op->type |= SETLK;
1298 if (branch_taken(word, regs, op))
1299 op->type |= BRTAKEN;
1305 op->type = RFI;
1309 op->type = BARRIER | BARRIER_ISYNC;
1320 op->type = COMPUTE + SETCC;
1327 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1335 op->type = BARRIER + BARRIER_SYNC;
1339 op->type = BARRIER + BARRIER_LWSYNC;
1342 op->type = BARRIER + BARRIER_PTESYNC;
1349 op->type = BARRIER + BARRIER_EIEIO;
1373 op->reg = rd;
1374 op->val = regs->gpr[rd];
1383 op->type = COMPUTE | PREFIXED;
1384 op->val = mlsd_8lsd_ea(word, suffix, regs);
1412 "=r" (op->val) : "r" (regs->gpr[ra]),
1418 "=r" (op->val) : "r" (regs->gpr[ra]),
1424 "=r" (op->val) : "r" (regs->gpr[ra]),
1437 op->val = regs->gpr[ra] * (short) word;
1442 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1452 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1462 do_cmp_signed(regs, op, val, imm, rd >> 2);
1467 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1472 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1473 set_cr0(regs, op);
1480 op->val = imm;
1487 op->val = imm;
1497 op->val = regs->nip + (imm << 16) + 4;
1500 op->type = UNKNOWN;
1508 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1515 op->val = ROTATE(val, rb) & MASK32(mb, me);
1523 op->val = ROTATE(val, rb) & MASK32(mb, me);
1527 op->val = regs->gpr[rd] | (unsigned short) word;
1532 op->val = regs->gpr[rd] | (imm << 16);
1536 op->val = regs->gpr[rd] ^ (unsigned short) word;
1541 op->val = regs->gpr[rd] ^ (imm << 16);
1545 op->val = regs->gpr[rd] & (unsigned short) word;
1546 set_cr0(regs, op);
1551 op->val = regs->gpr[rd] & (imm << 16);
1552 set_cr0(regs, op);
1577 op->val = val;
1584 op->val = val & MASK64_L(mb);
1587 op->val = val & MASK64_R(mb);
1592 op->type = UNKNOWN; /* illegal instruction */
1602 op->val = (val) ? val2 : regs->gpr[rb];
1622 op->type = MFMSR;
1623 op->reg = rd;
1628 op->type = MTMSR;
1629 op->reg = rd;
1630 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1636 op->type = MTMSR;
1637 op->reg = rd;
1641 op->val = imm;
1655 op->val = regs->ccr & imm;
1659 op->type = COMPUTE + SETCC;
1662 op->ccval = regs->ccr;
1665 op->ccval = (op->ccval & ~imm) |
1673 op->type = MFSPR;
1674 op->reg = rd;
1675 op->spr = spr;
1683 op->type = MTSPR;
1684 op->val = regs->gpr[rd];
1685 op->spr = spr;
1704 do_cmp_signed(regs, op, val, val2, rd >> 2);
1717 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1721 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1728 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1733 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1738 add_with_carry(regs, op, rd, regs->gpr[ra],
1743 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1748 op->val = regs->gpr[rb] - regs->gpr[ra];
1752 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1757 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1762 op->val = -regs->gpr[ra];
1766 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1771 add_with_carry(regs, op, rd, regs->gpr[ra],
1776 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1781 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1786 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1791 op->val = regs->gpr[ra] * regs->gpr[rb];
1795 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1800 op->val = (long)(int) regs->gpr[ra] *
1808 op->val = regs->gpr[ra] % regs->gpr[rb];
1812 op->val = regs->gpr[ra] + regs->gpr[rb];
1818 op->val = (unsigned int) regs->gpr[ra] %
1823 op->val = regs->gpr[ra] / regs->gpr[rb];
1827 op->val = (unsigned int) regs->gpr[ra] /
1832 op->val = (long int) regs->gpr[ra] /
1837 op->val = (int) regs->gpr[ra] /
1843 "=r" (op->val) : "r" (regs->gpr[ra]),
1848 "=r" (op->val) : "r" (regs->gpr[ra]),
1858 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1863 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1868 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1877 op->val = (long int) regs->gpr[ra] %
1884 op->val = (int) regs->gpr[ra] %
1894 op->val = ( val ? __builtin_clz(val) : 32 );
1899 op->val = ( val ? __builtin_clzl(val) : 64 );
1903 op->val = regs->gpr[rd] & regs->gpr[rb];
1907 op->val = regs->gpr[rd] & ~regs->gpr[rb];
1911 do_popcnt(regs, op, regs->gpr[rd], 8);
1915 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1919 do_prty(regs, op, regs->gpr[rd], 32);
1923 do_prty(regs, op, regs->gpr[rd], 64);
1927 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1931 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1935 op->val = regs->gpr[rd] ^ regs->gpr[rb];
1939 do_popcnt(regs, op, regs->gpr[rd], 32);
1943 op->val = regs->gpr[rd] | ~regs->gpr[rb];
1947 op->val = regs->gpr[rd] | regs->gpr[rb];
1951 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1955 do_popcnt(regs, op, regs->gpr[rd], 64);
1962 op->val = (val ? __builtin_ctz(val) : 32);
1969 op->val = (val ? __builtin_ctzl(val) : 64);
1973 op->val = (signed short) regs->gpr[rd];
1977 op->val = (signed char) regs->gpr[rd];
1981 op->val = (signed int) regs->gpr[rd];
1991 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1993 op->val = 0;
1999 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
2001 op->val = 0;
2005 op->type = COMPUTE + SETREG + SETXER;
2008 op->val = ival >> (sh < 32 ? sh : 31);
2009 op->xerval = regs->xer;
2011 op->xerval |= XER_CA;
2013 op->xerval &= ~XER_CA;
2014 set_ca32(op, op->xerval & XER_CA);
2018 op->type = COMPUTE + SETREG + SETXER;
2021 op->val = ival >> sh;
2022 op->xerval = regs->xer;
2024 op->xerval |= XER_CA;
2026 op->xerval &= ~XER_CA;
2027 set_ca32(op, op->xerval & XER_CA);
2034 op->val = regs->gpr[rd] << sh;
2036 op->val = 0;
2042 op->val = regs->gpr[rd] >> sh;
2044 op->val = 0;
2048 op->type = COMPUTE + SETREG + SETXER;
2051 op->val = ival >> (sh < 64 ? sh : 63);
2052 op->xerval = regs->xer;
2054 op->xerval |= XER_CA;
2056 op->xerval &= ~XER_CA;
2057 set_ca32(op, op->xerval & XER_CA);
2062 op->type = COMPUTE + SETREG + SETXER;
2065 op->val = ival >> sh;
2066 op->xerval = regs->xer;
2068 op->xerval |= XER_CA;
2070 op->xerval &= ~XER_CA;
2071 set_ca32(op, op->xerval & XER_CA);
2078 op->type = COMPUTE + SETREG;
2082 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2084 op->val = val;
2093 op->type = MKOP(CACHEOP, DCBST, 0);
2094 op->ea = xform_ea(word, regs);
2098 op->type = MKOP(CACHEOP, DCBF, 0);
2099 op->ea = xform_ea(word, regs);
2103 op->type = MKOP(CACHEOP, DCBTST, 0);
2104 op->ea = xform_ea(word, regs);
2105 op->reg = rd;
2109 op->type = MKOP(CACHEOP, DCBTST, 0);
2110 op->ea = xform_ea(word, regs);
2111 op->reg = rd;
2115 op->type = MKOP(CACHEOP, ICBI, 0);
2116 op->ea = xform_ea(word, regs);
2120 op->type = MKOP(CACHEOP, DCBZ, 0);
2121 op->ea = xform_ea(word, regs);
2130 op->type = UNKNOWN;
2131 op->update_reg = ra;
2132 op->reg = rd;
2133 op->val = regs->gpr[rd];
2135 op->vsx_flags = 0;
2140 op->ea = xform_ea(word, regs);
2143 op->type = MKOP(LARX, 0, 4);
2147 op->type = MKOP(STCX, 0, 4);
2152 op->type = MKOP(LARX, 0, 8);
2156 op->type = MKOP(STCX, 0, 8);
2160 op->type = MKOP(LARX, 0, 1);
2164 op->type = MKOP(STCX, 0, 1);
2168 op->type = MKOP(LARX, 0, 2);
2172 op->type = MKOP(STCX, 0, 2);
2177 op->type = MKOP(LARX, 0, 16);
2182 op->type = MKOP(STCX, 0, 16);
2188 op->type = MKOP(LOAD, u, 4);
2193 op->type = MKOP(LOAD, u, 1);
2202 op->type = MKOP(LOAD_VMX, 0, 1);
2203 op->element_size = 1;
2207 op->type = MKOP(LOAD_VMX, 0, 2);
2208 op->element_size = 2;
2212 op->type = MKOP(LOAD_VMX, 0, 4);
2213 op->element_size = 4;
2218 op->type = MKOP(LOAD_VMX, 0, 16);
2219 op->element_size = 16;
2223 op->type = MKOP(STORE_VMX, 0, 1);
2224 op->element_size = 1;
2228 op->type = MKOP(STORE_VMX, 0, 2);
2229 op->element_size = 2;
2233 op->type = MKOP(STORE_VMX, 0, 4);
2234 op->element_size = 4;
2239 op->type = MKOP(STORE_VMX, 0, 16);
2246 op->type = MKOP(LOAD, u, 8);
2251 op->type = MKOP(STORE, u, 8);
2257 op->type = MKOP(STORE, u, 4);
2262 op->type = MKOP(STORE, u, 1);
2267 op->type = MKOP(LOAD, u, 2);
2273 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2279 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2284 op->type = MKOP(STORE, u, 2);
2289 op->type = MKOP(LOAD, BYTEREV, 8);
2294 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2298 op->type = MKOP(LOAD, BYTEREV, 4);
2304 op->type = MKOP(LOAD_MULTI, 0, rb);
2305 op->ea = ra ? regs->gpr[ra] : 0;
2311 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2316 op->type = MKOP(LOAD_FP, u, 8);
2321 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2326 op->type = MKOP(STORE_FP, u, 8);
2331 op->type = MKOP(LOAD_FP, 0, 16);
2335 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2339 op->type = MKOP(LOAD_FP, 0, 4);
2343 op->type = MKOP(STORE_FP, 0, 16);
2347 op->type = MKOP(STORE_FP, 0, 4);
2354 op->type = MKOP(STORE, BYTEREV, 8);
2355 op->val = byterev_8(regs->gpr[rd]);
2360 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2364 op->type = MKOP(STORE, BYTEREV, 4);
2365 op->val = byterev_4(regs->gpr[rd]);
2371 op->type = MKOP(STORE_MULTI, 0, rb);
2372 op->ea = ra ? regs->gpr[ra] : 0;
2376 op->type = MKOP(LOAD, BYTEREV, 2);
2380 op->type = MKOP(STORE, BYTEREV, 2);
2381 op->val = byterev_2(regs->gpr[rd]);
2386 op->reg = rd | ((word & 1) << 5);
2387 op->type = MKOP(LOAD_VSX, 0, 4);
2388 op->element_size = 8;
2392 op->reg = rd | ((word & 1) << 5);
2393 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2394 op->element_size = 8;
2398 op->reg = rd | ((word & 1) << 5);
2399 op->type = MKOP(STORE_VSX, 0, 4);
2400 op->element_size = 8;
2406 op->reg = rd | ((word & 1) << 5);
2407 op->type = MKOP(LOAD_VSX, 0, 16);
2408 op->element_size = 16;
2409 op->vsx_flags = VSX_CHECK_VEC;
2417 op->reg = rd | ((word & 1) << 5);
2418 op->ea = ra ? regs->gpr[ra] : 0;
2422 op->type = MKOP(LOAD_VSX, 0, nb);
2423 op->element_size = 16;
2424 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2429 op->reg = rd | ((word & 1) << 5);
2430 op->type = MKOP(LOAD_VSX, 0, 8);
2431 op->element_size = 8;
2432 op->vsx_flags = VSX_SPLAT;
2438 op->reg = rd | ((word & 1) << 5);
2439 op->type = MKOP(LOAD_VSX, 0, 4);
2440 op->element_size = 4;
2441 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2447 op->reg = rd | ((word & 1) << 5);
2448 op->type = MKOP(STORE_VSX, 0, 16);
2449 op->element_size = 16;
2450 op->vsx_flags = VSX_CHECK_VEC;
2458 op->reg = rd | ((word & 1) << 5);
2459 op->ea = ra ? regs->gpr[ra] : 0;
2463 op->type = MKOP(STORE_VSX, 0, nb);
2464 op->element_size = 16;
2465 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2470 op->reg = rd | ((word & 1) << 5);
2471 op->type = MKOP(LOAD_VSX, 0, 4);
2472 op->element_size = 8;
2473 op->vsx_flags = VSX_FPCONV;
2477 op->reg = rd | ((word & 1) << 5);
2478 op->type = MKOP(LOAD_VSX, 0, 8);
2479 op->element_size = 8;
2483 op->reg = rd | ((word & 1) << 5);
2484 op->type = MKOP(STORE_VSX, 0, 4);
2485 op->element_size = 8;
2486 op->vsx_flags = VSX_FPCONV;
2490 op->reg = rd | ((word & 1) << 5);
2491 op->type = MKOP(STORE_VSX, 0, 8);
2492 op->element_size = 8;
2496 op->reg = rd | ((word & 1) << 5);
2497 op->type = MKOP(LOAD_VSX, 0, 16);
2498 op->element_size = 4;
2504 op->reg = rd | ((word & 1) << 5);
2505 op->type = MKOP(LOAD_VSX, 0, 1);
2506 op->element_size = 8;
2507 op->vsx_flags = VSX_CHECK_VEC;
2513 op->reg = rd | ((word & 1) << 5);
2514 op->type = MKOP(LOAD_VSX, 0, 16);
2515 op->element_size = 2;
2516 op->vsx_flags = VSX_CHECK_VEC;
2522 op->reg = rd | ((word & 1) << 5);
2523 op->type = MKOP(LOAD_VSX, 0, 2);
2524 op->element_size = 8;
2525 op->vsx_flags = VSX_CHECK_VEC;
2529 op->reg = rd | ((word & 1) << 5);
2530 op->type = MKOP(LOAD_VSX, 0, 16);
2531 op->element_size = 8;
2537 op->reg = rd | ((word & 1) << 5);
2538 op->type = MKOP(LOAD_VSX, 0, 16);
2539 op->element_size = 1;
2540 op->vsx_flags = VSX_CHECK_VEC;
2544 op->reg = rd | ((word & 1) << 5);
2545 op->type = MKOP(STORE_VSX, 0, 16);
2546 op->element_size = 4;
2552 op->reg = rd | ((word & 1) << 5);
2553 op->type = MKOP(STORE_VSX, 0, 1);
2554 op->element_size = 8;
2555 op->vsx_flags = VSX_CHECK_VEC;
2561 op->reg = rd | ((word & 1) << 5);
2562 op->type = MKOP(STORE_VSX, 0, 16);
2563 op->element_size = 2;
2564 op->vsx_flags = VSX_CHECK_VEC;
2570 op->reg = rd | ((word & 1) << 5);
2571 op->type = MKOP(STORE_VSX, 0, 2);
2572 op->element_size = 8;
2573 op->vsx_flags = VSX_CHECK_VEC;
2577 op->reg = rd | ((word & 1) << 5);
2578 op->type = MKOP(STORE_VSX, 0, 16);
2579 op->element_size = 8;
2585 op->reg = rd | ((word & 1) << 5);
2586 op->type = MKOP(STORE_VSX, 0, 16);
2587 op->element_size = 1;
2588 op->vsx_flags = VSX_CHECK_VEC;
2597 op->type = MKOP(LOAD, u, 4);
2598 op->ea = dform_ea(word, regs);
2603 op->type = MKOP(LOAD, u, 1);
2604 op->ea = dform_ea(word, regs);
2609 op->type = MKOP(STORE, u, 4);
2610 op->ea = dform_ea(word, regs);
2615 op->type = MKOP(STORE, u, 1);
2616 op->ea = dform_ea(word, regs);
2621 op->type = MKOP(LOAD, u, 2);
2622 op->ea = dform_ea(word, regs);
2627 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2628 op->ea = dform_ea(word, regs);
2633 op->type = MKOP(STORE, u, 2);
2634 op->ea = dform_ea(word, regs);
2640 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2641 op->ea = dform_ea(word, regs);
2645 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2646 op->ea = dform_ea(word, regs);
2652 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2653 op->ea = dform_ea(word, regs);
2658 op->type = MKOP(LOAD_FP, u, 8);
2659 op->ea = dform_ea(word, regs);
2664 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2665 op->ea = dform_ea(word, regs);
2670 op->type = MKOP(STORE_FP, u, 8);
2671 op->ea = dform_ea(word, regs);
2678 op->type = MKOP(LOAD, 0, 16);
2679 op->ea = dqform_ea(word, regs);
2685 op->ea = dsform_ea(word, regs);
2690 op->type = MKOP(LOAD_FP, 0, 16);
2695 op->reg = rd + 32;
2696 op->type = MKOP(LOAD_VSX, 0, 8);
2697 op->element_size = 8;
2698 op->vsx_flags = VSX_CHECK_VEC;
2703 op->reg = rd + 32;
2704 op->type = MKOP(LOAD_VSX, 0, 4);
2705 op->element_size = 8;
2706 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2714 op->ea = dsform_ea(word, regs);
2717 op->type = MKOP(LOAD, 0, 8);
2720 op->type = MKOP(LOAD, UPDATE, 8);
2723 op->type = MKOP(LOAD, SIGNEXT, 4);
2734 op->ea = dsform_ea(word, regs);
2735 op->type = MKOP(STORE_FP, 0, 16);
2741 op->ea = dqform_ea(word, regs);
2743 op->reg = rd + 32;
2744 op->type = MKOP(LOAD_VSX, 0, 16);
2745 op->element_size = 16;
2746 op->vsx_flags = VSX_CHECK_VEC;
2753 op->ea = dsform_ea(word, regs);
2754 op->reg = rd + 32;
2755 op->type = MKOP(STORE_VSX, 0, 8);
2756 op->element_size = 8;
2757 op->vsx_flags = VSX_CHECK_VEC;
2764 op->ea = dsform_ea(word, regs);
2765 op->reg = rd + 32;
2766 op->type = MKOP(STORE_VSX, 0, 4);
2767 op->element_size = 8;
2768 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2774 op->ea = dqform_ea(word, regs);
2776 op->reg = rd + 32;
2777 op->type = MKOP(STORE_VSX, 0, 16);
2778 op->element_size = 16;
2779 op->vsx_flags = VSX_CHECK_VEC;
2787 op->ea = dsform_ea(word, regs);
2790 op->type = MKOP(STORE, 0, 8);
2793 op->type = MKOP(STORE, UPDATE, 8);
2797 op->type = MKOP(STORE, 0, 16);
2807 op->update_reg = ra;
2809 op->reg = rd;
2810 op->val = regs->gpr[rd];
2818 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2821 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2825 op->reg = rd + 32;
2826 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2827 op->element_size = 8;
2828 op->vsx_flags = VSX_CHECK_VEC;
2831 op->reg = rd + 32;
2832 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2833 op->element_size = 8;
2834 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2837 op->reg = rd + 32;
2838 op->type = MKOP(STORE_VSX, PREFIXED, 8);
2839 op->element_size = 8;
2840 op->vsx_flags = VSX_CHECK_VEC;
2843 op->reg = rd + 32;
2844 op->type = MKOP(STORE_VSX, PREFIXED, 4);
2845 op->element_size = 8;
2846 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2849 op->reg += 32;
2852 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
2853 op->element_size = 16;
2854 op->vsx_flags = VSX_CHECK_VEC;
2857 op->reg = rd + 32;
2860 op->type = MKOP(STORE_VSX, PREFIXED, 16);
2861 op->element_size = 16;
2862 op->vsx_flags = VSX_CHECK_VEC;
2866 op->type = MKOP(LOAD, PREFIXED, 16);
2869 op->type = MKOP(LOAD, PREFIXED, 8);
2872 op->type = MKOP(STORE, PREFIXED, 16);
2875 op->type = MKOP(STORE, PREFIXED, 8);
2884 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2887 op->type = MKOP(LOAD, PREFIXED, 4);
2890 op->type = MKOP(LOAD, PREFIXED, 1);
2893 op->type = MKOP(STORE, PREFIXED, 4);
2896 op->type = MKOP(STORE, PREFIXED, 1);
2899 op->type = MKOP(LOAD, PREFIXED, 2);
2902 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
2905 op->type = MKOP(STORE, PREFIXED, 2);
2908 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
2911 op->type = MKOP(LOAD_FP, PREFIXED, 8);
2914 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
2917 op->type = MKOP(STORE_FP, PREFIXED, 8);
2928 if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) {
2929 switch (GETTYPE(op->type)) {
2943 if ((GETTYPE(op->type) == LOAD_VSX ||
2944 GETTYPE(op->type) == STORE_VSX) &&
2953 op->type = UNKNOWN;
2958 set_cr0(regs, op);
2960 op->reg = ra;
2961 op->type |= SETREG;
2966 set_cr0(regs, op);
2968 op->reg = rd;
2969 op->type |= SETREG;
2973 op->type = INTERRUPT | 0x700;
2974 op->val = SRR1_PROGPRIV;
2978 op->type = INTERRUPT | 0x700;
2979 op->val = SRR1_PROGTRAP;
3046 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3050 next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3051 switch (GETTYPE(op->type)) {
3053 if (op->type & SETREG)
3054 regs->gpr[op->reg] = op->val;
3055 if (op->type & SETCC)
3056 regs->ccr = op->ccval;
3057 if (op->type & SETXER)
3058 regs->xer = op->xerval;
3062 if (op->type & SETLK)
3064 if (op->type & BRTAKEN)
3065 next_pc = op->val;
3066 if (op->type & DECCTR)
3071 switch (op->type & BARRIER_MASK) {
3093 switch (op->spr) {
3095 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3098 regs->gpr[op->reg] = regs->link;
3101 regs->gpr[op->reg] = regs->ctr;
3109 switch (op->spr) {
3111 regs->xer = op->val & 0xffffffffUL;
3114 regs->link = op->val;
3117 regs->ctr = op->val;
3138 * -EINVAL = unknown operation in *op
3140 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3150 size = GETSIZE(op->type);
3151 type = GETTYPE(op->type);
3153 ea = truncate_if_32bit(regs->msr, op->ea);
3180 err = do_lqarx(ea, ®s->gpr[op->reg]);
3191 regs->gpr[op->reg] = val;
3203 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3206 __put_user_asmx(op->val, ea, err, "sthcx.", cr);
3210 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3214 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3217 err = do_stqcx(ea, regs->gpr[op->reg],
3218 regs->gpr[op->reg + 1], &cr);
3235 err = emulate_lq(regs, ea, op->reg, cross_endian);
3239 err = read_mem(®s->gpr[op->reg], ea, size, regs);
3241 if (op->type & SIGNEXT)
3242 do_signext(®s->gpr[op->reg], size);
3243 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3244 do_byterev(®s->gpr[op->reg], size);
3258 err = do_fp_load(op, ea, regs, cross_endian);
3265 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3276 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3280 err = do_vsx_load(op, ea, regs, cross_endian);
3287 rd = op->reg;
3309 err = emulate_stq(regs, ea, op->reg, cross_endian);
3313 if ((op->type & UPDATE) && size == sizeof(long) &&
3314 op->reg == 1 && op->update_reg == 1 &&
3321 do_byterev(&op->val, size);
3322 err = write_mem(op->val, ea, size, regs);
3329 err = do_fp_store(op, ea, regs, cross_endian);
3336 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3347 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3351 err = do_vsx_store(op, ea, regs, cross_endian);
3358 rd = op->reg;
3383 if (op->type & UPDATE)
3384 regs->gpr[op->update_reg] = op->ea;
3399 struct instruction_op op;
3404 r = analyse_instr(&op, regs, instr);
3408 emulate_update_regs(regs, &op);
3413 type = GETTYPE(op.type);
3416 err = emulate_loadstore(regs, &op);
3424 ea = truncate_if_32bit(regs->msr, op.ea);
3427 switch (op.type & CACHEOP_MASK) {
3435 if (op.reg == 0)
3439 if (op.reg == 0)
3456 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3460 val = regs->gpr[op.reg];
3464 /* here op.val is the mask of bits to change */
3465 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3509 regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));