Lines Matching refs:src

221 	struct irq_source src[MAX_IRQ];
303 irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);
305 if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
307 priority = IVPR_PRIORITY(opp->src[irq].ivpr);
327 struct irq_source *src;
331 src = &opp->src[n_IRQ];
336 if (src->output != ILR_INTTGT_INT) {
338 __func__, src->output, n_IRQ, active, was_active,
339 dst->outputs_active[src->output]);
347 dst->outputs_active[src->output]++ == 0) {
349 __func__, src->output, n_CPU, n_IRQ);
350 mpic_irq_raise(opp, dst, src->output);
354 --dst->outputs_active[src->output] == 0) {
356 __func__, src->output, n_CPU, n_IRQ);
357 mpic_irq_lower(opp, dst, src->output);
364 priority = IVPR_PRIORITY(src->ivpr);
413 struct irq_source *src;
417 src = &opp->src[n_IRQ];
418 active = src->pending;
420 if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) {
426 was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK);
438 src->ivpr |= IVPR_ACTIVITY_MASK;
440 src->ivpr &= ~IVPR_ACTIVITY_MASK;
442 if (src->destmask == 0) {
448 if (src->destmask == (1 << src->last_cpu)) {
450 IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active);
451 } else if (!(src->ivpr & IVPR_MODE_MASK)) {
454 if (src->destmask & (1 << i)) {
461 for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
465 if (src->destmask & (1 << i)) {
468 src->last_cpu = i;
478 struct irq_source *src;
485 src = &opp->src[n_IRQ];
487 n_IRQ, level, src->ivpr);
488 if (src->level) {
490 src->pending = level;
495 src->pending = 1;
499 if (src->output != ILR_INTTGT_INT) {
506 src->pending = 0;
526 opp->src[i].ivpr = opp->ivpr_reset;
528 switch (opp->src[i].type) {
530 opp->src[i].level =
535 opp->src[i].ivpr |= IVPR_POLARITY_MASK;
563 return opp->src[n_IRQ].idr;
569 return opp->src[n_IRQ].output;
576 return opp->src[n_IRQ].ivpr;
582 struct irq_source *src = &opp->src[n_IRQ];
594 src->idr = val & mask;
595 pr_debug("Set IDR %d to 0x%08x\n", n_IRQ, src->idr);
598 if (src->idr & crit_mask) {
599 if (src->idr & normal_mask) {
604 src->output = ILR_INTTGT_CINT;
605 src->nomask = true;
606 src->destmask = 0;
611 if (src->idr & (1UL << n_ci))
612 src->destmask |= 1UL << i;
615 src->output = ILR_INTTGT_INT;
616 src->nomask = false;
617 src->destmask = src->idr & normal_mask;
620 src->destmask = src->idr;
628 struct irq_source *src = &opp->src[n_IRQ];
630 src->output = val & ILR_INTTGT_MASK;
631 pr_debug("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr,
632 src->output);
650 opp->src[n_IRQ].ivpr =
651 (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
657 switch (opp->src[n_IRQ].type) {
659 opp->src[n_IRQ].level =
660 !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK);
664 opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK;
668 opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK);
674 opp->src[n_IRQ].ivpr);
1027 struct irq_source *src;
1049 opp->src[opp->irq_ipi0 + idx].destmask |= val;
1096 src = &opp->src[n_IRQ];
1099 IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) {
1129 struct irq_source *src;
1142 src = &opp->src[irq];
1143 if (!(src->ivpr & IVPR_ACTIVITY_MASK) ||
1144 !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) {
1146 __func__, irq, dst->ctpr, src->ivpr);
1152 retval = IVPR_VECTOR(opp, src->ivpr);
1155 if (!src->level) {
1157 src->ivpr &= ~IVPR_ACTIVITY_MASK;
1158 src->pending = 0;
1163 src->destmask &= ~(1 << cpu);
1164 if (src->destmask && !src->level) {
1169 src->ivpr |= IVPR_ACTIVITY_MASK;
1324 opp->src[i].level = false;
1328 opp->src[i].type = IRQ_TYPE_FSLINT;
1329 opp->src[i].level = true;
1334 opp->src[i].type = IRQ_TYPE_FSLSPECIAL;
1335 opp->src[i].level = false;
1595 attr32 = opp->src[attr->attr].pending;