Lines Matching refs:opp
128 static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
171 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
241 static void mpic_irq_raise(struct openpic *opp, struct irq_dest *dst,
250 __func__, (int)(dst - &opp->dst[0]));
263 static void mpic_irq_lower(struct openpic *opp, struct irq_dest *dst,
268 __func__, (int)(dst - &opp->dst[0]));
291 static void IRQ_check(struct openpic *opp, struct irq_queue *q)
298 irq = find_next_bit(q->queue, opp->max_irq, irq + 1);
299 if (irq == opp->max_irq)
303 irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);
305 if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
307 priority = IVPR_PRIORITY(opp->src[irq].ivpr);
315 static int IRQ_get_next(struct openpic *opp, struct irq_queue *q)
318 IRQ_check(opp, q);
323 static void IRQ_local_pipe(struct openpic *opp, int n_CPU, int n_IRQ,
330 dst = &opp->dst[n_CPU];
331 src = &opp->src[n_IRQ];
350 mpic_irq_raise(opp, dst, src->output);
357 mpic_irq_lower(opp, dst, src->output);
374 IRQ_check(opp, &dst->raised);
383 if (IRQ_get_next(opp, &dst->servicing) >= 0 &&
390 mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
393 IRQ_get_next(opp, &dst->servicing);
405 mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
411 static void openpic_update_irq(struct openpic *opp, int n_IRQ)
417 src = &opp->src[n_IRQ];
450 IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active);
453 for (i = 0; i < opp->nb_cpus; i++) {
455 IRQ_local_pipe(opp, i, n_IRQ, active,
462 if (i == opp->nb_cpus)
466 IRQ_local_pipe(opp, i, n_IRQ, active,
477 struct openpic *opp = opaque;
485 src = &opp->src[n_IRQ];
491 openpic_update_irq(opp, n_IRQ);
496 openpic_update_irq(opp, n_IRQ);
507 openpic_update_irq(opp, n_IRQ);
512 static void openpic_reset(struct openpic *opp)
516 opp->gcr = GCR_RESET;
518 opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) |
519 (opp->vid << FRR_VID_SHIFT);
521 opp->pir = 0;
522 opp->spve = -1 & opp->vector_mask;
523 opp->tfrr = opp->tfrr_reset;
525 for (i = 0; i < opp->max_irq; i++) {
526 opp->src[i].ivpr = opp->ivpr_reset;
528 switch (opp->src[i].type) {
530 opp->src[i].level =
531 !!(opp->ivpr_reset & IVPR_SENSE_MASK);
535 opp->src[i].ivpr |= IVPR_POLARITY_MASK;
542 write_IRQreg_idr(opp, i, opp->idr_reset);
546 opp->dst[i].ctpr = 15;
547 memset(&opp->dst[i].raised, 0, sizeof(struct irq_queue));
548 opp->dst[i].raised.next = -1;
549 memset(&opp->dst[i].servicing, 0, sizeof(struct irq_queue));
550 opp->dst[i].servicing.next = -1;
554 opp->timers[i].tccr = 0;
555 opp->timers[i].tbcr = TBCR_CI;
558 opp->gcr = 0;
561 static inline uint32_t read_IRQreg_idr(struct openpic *opp, int n_IRQ)
563 return opp->src[n_IRQ].idr;
566 static inline uint32_t read_IRQreg_ilr(struct openpic *opp, int n_IRQ)
568 if (opp->flags & OPENPIC_FLAG_ILR)
569 return opp->src[n_IRQ].output;
574 static inline uint32_t read_IRQreg_ivpr(struct openpic *opp, int n_IRQ)
576 return opp->src[n_IRQ].ivpr;
579 static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
582 struct irq_source *src = &opp->src[n_IRQ];
583 uint32_t normal_mask = (1UL << opp->nb_cpus) - 1;
586 int crit_shift = IDR_EP_SHIFT - opp->nb_cpus;
589 if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
597 if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
608 for (i = 0; i < opp->nb_cpus; i++) {
624 static inline void write_IRQreg_ilr(struct openpic *opp, int n_IRQ,
627 if (opp->flags & OPENPIC_FLAG_ILR) {
628 struct irq_source *src = &opp->src[n_IRQ];
638 static inline void write_IRQreg_ivpr(struct openpic *opp, int n_IRQ,
647 IVPR_POLARITY_MASK | opp->vector_mask;
650 opp->src[n_IRQ].ivpr =
651 (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
657 switch (opp->src[n_IRQ].type) {
659 opp->src[n_IRQ].level =
660 !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK);
664 opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK;
668 opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK);
672 openpic_update_irq(opp, n_IRQ);
674 opp->src[n_IRQ].ivpr);
677 static void openpic_gcr_write(struct openpic *opp, uint64_t val)
680 openpic_reset(opp);
684 opp->gcr &= ~opp->mpic_mode_mask;
685 opp->gcr |= val & opp->mpic_mode_mask;
690 struct openpic *opp = opaque;
708 err = openpic_cpu_write_internal(opp, addr, val,
714 openpic_gcr_write(opp, val);
731 write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val);
735 opp->spve = val & opp->vector_mask;
746 struct openpic *opp = opaque;
757 retval = opp->frr;
758 retval |= (opp->nb_cpus - 1) << FRR_NCPU_SHIFT;
761 retval = opp->gcr;
764 retval = opp->vir;
770 retval = opp->brr1;
780 err = openpic_cpu_read_internal(opp, addr,
790 retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx);
794 retval = opp->spve;
808 struct openpic *opp = opaque;
819 opp->tfrr = val;
830 if ((opp->timers[idx].tccr & TCCR_TOG) != 0 &&
832 (opp->timers[idx].tbcr & TBCR_CI) != 0)
833 opp->timers[idx].tccr &= ~TCCR_TOG;
835 opp->timers[idx].tbcr = val;
838 write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val);
841 write_IRQreg_idr(opp, opp->irq_tim0 + idx, val);
850 struct openpic *opp = opaque;
861 retval = opp->tfrr;
867 retval = opp->timers[idx].tccr;
870 retval = opp->timers[idx].tbcr;
873 retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);
876 retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);
888 struct openpic *opp = opaque;
898 write_IRQreg_ivpr(opp, idx, val);
901 write_IRQreg_idr(opp, idx, val);
904 write_IRQreg_ilr(opp, idx, val);
913 struct openpic *opp = opaque;
925 retval = read_IRQreg_ivpr(opp, idx);
928 retval = read_IRQreg_idr(opp, idx);
931 retval = read_IRQreg_ilr(opp, idx);
942 struct openpic *opp = opaque;
943 int idx = opp->irq_msi;
955 opp->msi[srs].msir |= 1 << ibs;
956 openpic_set_irq(opp, idx, 1);
968 struct openpic *opp = opaque;
987 r = opp->msi[srs].msir;
989 opp->msi[srs].msir = 0;
990 openpic_set_irq(opp, opp->irq_msi + srs, 0);
994 r |= (opp->msi[i].msir ? 1 : 0) << i;
1026 struct openpic *opp = opaque;
1040 dst = &opp->dst[idx];
1049 opp->src[opp->irq_ipi0 + idx].destmask |= val;
1050 openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
1051 openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
1063 mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
1067 mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
1081 s_IRQ = IRQ_get_next(opp, &dst->servicing);
1093 s_IRQ = IRQ_get_next(opp, &dst->servicing);
1095 n_IRQ = IRQ_get_next(opp, &dst->raised);
1096 src = &opp->src[n_IRQ];
1102 mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
1105 spin_unlock(&opp->lock);
1106 kvm_notify_acked_irq(opp->kvm, 0, notify_eoi);
1107 spin_lock(&opp->lock);
1120 struct openpic *opp = opaque;
1122 return openpic_cpu_write_internal(opp, addr, val,
1126 static uint32_t openpic_iack(struct openpic *opp, struct irq_dest *dst,
1133 mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
1135 irq = IRQ_get_next(opp, &dst->raised);
1140 return opp->spve;
1142 src = &opp->src[irq];
1147 openpic_update_irq(opp, irq);
1148 retval = opp->spve;
1152 retval = IVPR_VECTOR(opp, src->ivpr);
1162 if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + MAX_IPI))) {
1166 openpic_set_irq(opp, irq, 1);
1167 openpic_set_irq(opp, irq, 0);
1178 struct openpic *opp = vcpu->arch.mpic;
1182 spin_lock_irqsave(&opp->lock, flags);
1184 if ((opp->gcr & opp->mpic_mode_mask) == GCR_MODE_PROXY)
1185 kvmppc_set_epr(vcpu, openpic_iack(opp, &opp->dst[cpu], cpu));
1187 spin_unlock_irqrestore(&opp->lock, flags);
1193 struct openpic *opp = opaque;
1206 dst = &opp->dst[idx];
1216 retval = openpic_iack(opp, dst, idx);
1233 struct openpic *opp = opaque;
1235 return openpic_cpu_read_internal(opp, addr, ptr,
1288 static void add_mmio_region(struct openpic *opp, const struct mem_reg *mr)
1290 if (opp->num_mmio_regions >= MAX_MMIO_REGIONS) {
1295 opp->mmio_regions[opp->num_mmio_regions++] = mr;
1298 static void fsl_common_init(struct openpic *opp)
1303 add_mmio_region(opp, &openpic_msi_mmio);
1304 add_mmio_region(opp, &openpic_summary_mmio);
1306 opp->vid = VID_REVISION_1_2;
1307 opp->vir = VIR_GENERIC;
1308 opp->vector_mask = 0xFFFF;
1309 opp->tfrr_reset = 0;
1310 opp->ivpr_reset = IVPR_MASK_MASK;
1311 opp->idr_reset = 1 << 0;
1312 opp->max_irq = MAX_IRQ;
1314 opp->irq_ipi0 = virq;
1316 opp->irq_tim0 = virq;
1321 opp->irq_msi = 224;
1323 for (i = 0; i < opp->fsl->max_ext; i++)
1324 opp->src[i].level = false;
1328 opp->src[i].type = IRQ_TYPE_FSLINT;
1329 opp->src[i].level = true;
1334 opp->src[i].type = IRQ_TYPE_FSLSPECIAL;
1335 opp->src[i].level = false;
1339 static int kvm_mpic_read_internal(struct openpic *opp, gpa_t addr, u32 *ptr)
1343 for (i = 0; i < opp->num_mmio_regions; i++) {
1344 const struct mem_reg *mr = opp->mmio_regions[i];
1349 return mr->read(opp, addr - mr->start_addr, ptr);
1355 static int kvm_mpic_write_internal(struct openpic *opp, gpa_t addr, u32 val)
1359 for (i = 0; i < opp->num_mmio_regions; i++) {
1360 const struct mem_reg *mr = opp->mmio_regions[i];
1365 return mr->write(opp, addr - mr->start_addr, val);
1375 struct openpic *opp = container_of(this, struct openpic, mmio);
1388 spin_lock_irq(&opp->lock);
1389 ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val);
1390 spin_unlock_irq(&opp->lock);
1417 struct openpic *opp = container_of(this, struct openpic, mmio);
1429 spin_lock_irq(&opp->lock);
1430 ret = kvm_mpic_write_internal(opp, addr - opp->reg_base,
1432 spin_unlock_irq(&opp->lock);
1445 static void map_mmio(struct openpic *opp)
1447 kvm_iodevice_init(&opp->mmio, &mpic_mmio_ops);
1449 kvm_io_bus_register_dev(opp->kvm, KVM_MMIO_BUS,
1450 opp->reg_base, OPENPIC_REG_SIZE,
1451 &opp->mmio);
1454 static void unmap_mmio(struct openpic *opp)
1456 kvm_io_bus_unregister_dev(opp->kvm, KVM_MMIO_BUS, &opp->mmio);
1459 static int set_base_addr(struct openpic *opp, struct kvm_device_attr *attr)
1472 if (base == opp->reg_base)
1475 mutex_lock(&opp->kvm->slots_lock);
1477 unmap_mmio(opp);
1478 opp->reg_base = base;
1486 map_mmio(opp);
1489 mutex_unlock(&opp->kvm->slots_lock);
1496 static int access_reg(struct openpic *opp, gpa_t addr, u32 *val, int type)
1503 spin_lock_irq(&opp->lock);
1506 ret = kvm_mpic_write_internal(opp, addr, *val);
1508 ret = kvm_mpic_read_internal(opp, addr, val);
1510 spin_unlock_irq(&opp->lock);
1519 struct openpic *opp = dev->private;
1526 return set_base_addr(opp, attr);
1535 return access_reg(opp, attr->attr, &attr32, ATTR_SET);
1547 spin_lock_irq(&opp->lock);
1548 openpic_set_irq(opp, attr->attr, attr32);
1549 spin_unlock_irq(&opp->lock);
1558 struct openpic *opp = dev->private;
1567 mutex_lock(&opp->kvm->slots_lock);
1568 attr64 = opp->reg_base;
1569 mutex_unlock(&opp->kvm->slots_lock);
1581 ret = access_reg(opp, attr->attr, &attr32, ATTR_GET);
1594 spin_lock_irq(&opp->lock);
1595 attr32 = opp->src[attr->attr].pending;
1596 spin_unlock_irq(&opp->lock);
1633 struct openpic *opp = dev->private;
1636 kfree(opp);
1640 static int mpic_set_default_irq_routing(struct openpic *opp)
1649 kvm_set_irq_routing(opp->kvm, routing, 0, 0);
1657 struct openpic *opp;
1664 opp = kzalloc(sizeof(struct openpic), GFP_KERNEL);
1665 if (!opp)
1668 dev->private = opp;
1669 opp->kvm = dev->kvm;
1670 opp->dev = dev;
1671 opp->model = type;
1672 spin_lock_init(&opp->lock);
1674 add_mmio_region(opp, &openpic_gbl_mmio);
1675 add_mmio_region(opp, &openpic_tmr_mmio);
1676 add_mmio_region(opp, &openpic_src_mmio);
1677 add_mmio_region(opp, &openpic_cpu_mmio);
1679 switch (opp->model) {
1681 opp->fsl = &fsl_mpic_20;
1682 opp->brr1 = 0x00400200;
1683 opp->flags |= OPENPIC_FLAG_IDR_CRIT;
1684 opp->nb_irqs = 80;
1685 opp->mpic_mode_mask = GCR_MODE_MIXED;
1687 fsl_common_init(opp);
1692 opp->fsl = &fsl_mpic_42;
1693 opp->brr1 = 0x00400402;
1694 opp->flags |= OPENPIC_FLAG_ILR;
1695 opp->nb_irqs = 196;
1696 opp->mpic_mode_mask = GCR_MODE_PROXY;
1698 fsl_common_init(opp);
1707 ret = mpic_set_default_irq_routing(opp);
1711 openpic_reset(opp);
1714 dev->kvm->arch.mpic = opp;
1719 kfree(opp);
1735 struct openpic *opp = dev->private;
1740 if (opp->kvm != vcpu->kvm)
1745 spin_lock_irq(&opp->lock);
1747 if (opp->dst[cpu].vcpu) {
1756 opp->dst[cpu].vcpu = vcpu;
1757 opp->nb_cpus = max(opp->nb_cpus, cpu + 1);
1759 vcpu->arch.mpic = opp;
1764 if (opp->mpic_mode_mask == GCR_MODE_PROXY)
1768 spin_unlock_irq(&opp->lock);
1777 void kvmppc_mpic_disconnect_vcpu(struct openpic *opp, struct kvm_vcpu *vcpu)
1779 BUG_ON(!opp->dst[vcpu->arch.irq_cpu_id].vcpu);
1781 opp->dst[vcpu->arch.irq_cpu_id].vcpu = NULL;
1795 struct openpic *opp = kvm->arch.mpic;
1798 spin_lock_irqsave(&opp->lock, flags);
1799 openpic_set_irq(opp, irq, level);
1800 spin_unlock_irqrestore(&opp->lock, flags);
1809 struct openpic *opp = kvm->arch.mpic;
1812 spin_lock_irqsave(&opp->lock, flags);
1819 spin_unlock_irqrestore(&opp->lock, flags);