Lines Matching refs:arch
26 vcpu->arch.regs.nip = vcpu->arch.shared->srr0;
27 kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
32 vcpu->arch.regs.nip = vcpu->arch.dsrr0;
33 kvmppc_set_msr(vcpu, vcpu->arch.dsrr1);
38 vcpu->arch.regs.nip = vcpu->arch.csrr0;
39 kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
80 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
90 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
96 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
127 vcpu->arch.shared->dar = spr_val;
130 vcpu->arch.shared->esr = spr_val;
133 vcpu->arch.csrr0 = spr_val;
136 vcpu->arch.csrr1 = spr_val;
139 vcpu->arch.dsrr0 = spr_val;
142 vcpu->arch.dsrr1 = spr_val;
153 vcpu->arch.dbg_reg.iac1 = spr_val;
164 vcpu->arch.dbg_reg.iac2 = spr_val;
176 vcpu->arch.dbg_reg.iac3 = spr_val;
187 vcpu->arch.dbg_reg.iac4 = spr_val;
199 vcpu->arch.dbg_reg.dac1 = spr_val;
210 vcpu->arch.dbg_reg.dac2 = spr_val;
225 vcpu->arch.dbg_reg.dbcr0 = spr_val;
236 vcpu->arch.dbg_reg.dbcr1 = spr_val;
247 vcpu->arch.dbg_reg.dbcr2 = spr_val;
257 vcpu->arch.dbsr &= ~spr_val;
258 if (!(vcpu->arch.dbsr & ~DBSR_IDE))
269 if (vcpu->arch.tcr & TCR_WRC_MASK) {
271 spr_val |= vcpu->arch.tcr & TCR_WRC_MASK;
277 vcpu->arch.decar = spr_val;
298 vcpu->arch.ivpr = spr_val;
304 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
307 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
310 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
316 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
319 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
322 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
325 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
328 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
331 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
337 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
340 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
343 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
346 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
349 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
352 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
355 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
358 vcpu->arch.mcsr &= ~spr_val;
364 mtspr(SPRN_EPCR, vcpu->arch.shadow_epcr);
373 current->thread.debug = vcpu->arch.dbg_reg;
374 switch_booke_debug_regs(&vcpu->arch.dbg_reg);
385 *spr_val = vcpu->arch.ivpr;
388 *spr_val = vcpu->arch.shared->dar;
391 *spr_val = vcpu->arch.shared->esr;
394 *spr_val = vcpu->arch.epr;
397 *spr_val = vcpu->arch.csrr0;
400 *spr_val = vcpu->arch.csrr1;
403 *spr_val = vcpu->arch.dsrr0;
406 *spr_val = vcpu->arch.dsrr1;
409 *spr_val = vcpu->arch.dbg_reg.iac1;
412 *spr_val = vcpu->arch.dbg_reg.iac2;
416 *spr_val = vcpu->arch.dbg_reg.iac3;
419 *spr_val = vcpu->arch.dbg_reg.iac4;
423 *spr_val = vcpu->arch.dbg_reg.dac1;
426 *spr_val = vcpu->arch.dbg_reg.dac2;
429 *spr_val = vcpu->arch.dbg_reg.dbcr0;
434 *spr_val = vcpu->arch.dbg_reg.dbcr1;
437 *spr_val = vcpu->arch.dbg_reg.dbcr2;
440 *spr_val = vcpu->arch.dbsr;
443 *spr_val = vcpu->arch.tsr;
446 *spr_val = vcpu->arch.tcr;
450 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
453 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
456 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
459 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
462 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
465 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
468 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
471 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
474 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
477 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
480 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
483 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
486 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
489 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
492 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
495 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
498 *spr_val = vcpu->arch.mcsr;
502 *spr_val = vcpu->arch.epcr;