Lines Matching refs:arch
19 u64 msr = vcpu->arch.shregs.msr;
21 tfiar = vcpu->arch.regs.nip & ~0x3ull;
23 if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr))
29 vcpu->arch.tfiar = tfiar;
31 vcpu->arch.texasr = (vcpu->arch.texasr & 0x3ffffff) | texasr;
37 * instruction image is in vcpu->arch.emul_inst. If the guest was in
44 u32 instr = vcpu->arch.emul_inst;
45 u64 msr = vcpu->arch.shregs.msr;
63 newmsr = vcpu->arch.shregs.srr1;
69 vcpu->arch.shregs.msr = newmsr;
70 vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
71 vcpu->arch.regs.nip = vcpu->arch.shregs.srr0;
75 if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
81 if (!(vcpu->arch.hfscr & HFSCR_EBB)) {
86 if ((msr & MSR_PR) && !(vcpu->arch.fscr & FSCR_EBB)) {
88 vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
93 bescr = vcpu->arch.bescr;
100 vcpu->arch.bescr = bescr;
102 vcpu->arch.shregs.msr = msr;
103 vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
104 vcpu->arch.regs.nip = vcpu->arch.ebbrr;
118 vcpu->arch.shregs.msr = newmsr;
123 /* check for PR=1 and arch 2.06 bit set in PCR */
124 if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
130 if (!(vcpu->arch.hfscr & HFSCR_TM)) {
137 vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
144 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
154 vcpu->arch.shregs.msr = msr;
160 if (!(vcpu->arch.hfscr & HFSCR_TM)) {
167 vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
179 if (!(vcpu->arch.orig_texasr & TEXASR_FS)) {
189 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
191 vcpu->arch.shregs.msr &= ~MSR_TS_MASK;
198 if (!(vcpu->arch.hfscr & HFSCR_TM)) {
205 vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |
212 if (MSR_TM_ACTIVE(msr) || !(vcpu->arch.texasr & TEXASR_FS)) {
220 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
222 vcpu->arch.shregs.msr = msr | MSR_TS_S;