Lines Matching defs:msr
19 u64 msr = vcpu->arch.shregs.msr;
23 if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr))
25 if (msr & MSR_PR) {
45 u64 msr = vcpu->arch.shregs.msr;
65 WARN_ON_ONCE(!(MSR_TM_SUSPENDED(msr) &&
69 vcpu->arch.shregs.msr = newmsr;
75 if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
86 if ((msr & MSR_PR) && !(vcpu->arch.fscr & FSCR_EBB)) {
95 WARN_ON_ONCE(!(MSR_TM_SUSPENDED(msr) &&
101 msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
102 vcpu->arch.shregs.msr = msr;
112 WARN_ON_ONCE(!(MSR_TM_SUSPENDED(msr) &&
116 newmsr = (newmsr & ~MSR_LE) | (msr & MSR_LE);
118 vcpu->arch.shregs.msr = newmsr;
124 if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
135 if (!(msr & MSR_TM)) {
145 (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
148 if (MSR_TM_SUSPENDED(msr))
149 msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
151 if (MSR_TM_TRANSACTIONAL(msr))
152 msr = (msr & ~MSR_TS_MASK) | MSR_TS_S;
154 vcpu->arch.shregs.msr = msr;
165 if (!(msr & MSR_TM)) {
174 if (!MSR_TM_ACTIVE(msr)) {
190 (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
191 vcpu->arch.shregs.msr &= ~MSR_TS_MASK;
203 if (!(msr & MSR_TM)) {
212 if (MSR_TM_ACTIVE(msr) || !(vcpu->arch.texasr & TEXASR_FS)) {
221 (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
222 vcpu->arch.shregs.msr = msr | MSR_TS_S;