Lines Matching refs:ull
412 #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
413 #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
414 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
415 #define MFC_CNTL_SUSPEND_MASK (1ull << 4)
416 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
417 #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
418 #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
419 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
420 #define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
421 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
422 #define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
423 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
424 #define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
425 #define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
426 #define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
427 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
428 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
429 #define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
430 #define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
431 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
432 #define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
433 #define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
434 #define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
612 #define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
613 #define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
618 #define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
663 #define SPU_ECC_CNTL_E (1ull << 0ull)
666 #define SPU_ECC_CNTL_S (1ull << 1ull)
669 #define SPU_ECC_CNTL_B (1ull << 2ull)
672 #define SPU_ECC_CNTL_I_SHIFT 3ull
673 #define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
675 #define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
676 #define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
677 #define SPU_ECC_CNTL_D (1ull << 5ull)
681 #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
682 #define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
683 #define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
684 #define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
685 #define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
686 #define SPU_ECC_DATA_ERROR (1ull << 5ul)
687 #define SPU_ECC_DMA_ERROR (1ull << 6ul)
688 #define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
691 #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
692 #define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)