Lines Matching refs:ori
38 l.ori gpr,gpr,lo(symbol)
265 l.ori r30,r30,(EXCEPTION_SR) ;\
278 * l.ori r3,r0,0x1 ;\
281 * l.ori r3,r3,lo(0xf0000100) ;\
302 l.ori r3,r0,lo(_string_unhandled_exception) ;\
308 l.ori r3,r0,lo(_string_epc_prefix) ;\
312 l.ori r3,r0,lo(_string_nl) ;\
347 l.ori r30,r0,(EXCEPTION_SR) ;\
521 l.ori r3,r0,0x1
579 l.ori r4,r0,0x0
620 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
646 l.ori r4,r4,lo(OF_DT_HEADER)
738 l.ori r25,r25,SPR_SR_IEE
743 l.ori r25,r25,0xffff
794 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
845 l.ori r30,r0,16
854 l.ori r30,r0,1
872 l.ori r6,r6,SPR_SR_ICE
911 l.ori r30,r0,16
920 l.ori r30,r0,1
934 l.ori r6,r6,SPR_SR_DCE
1006 l.ori r5, r0, 0x1
1012 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1014 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1026 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1028 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1093 l.ori r5, r0, 0x1
1099 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1101 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1119 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1121 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1206 l.ori r3, r0, 0x1
1218 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1291 l.ori r3, r0, 0x1
1306 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1313 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1394 * a9 29 bb bb l.ori r9,0xbbbb
1402 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1407 // l.ori r9,0xbbbb
1408 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1445 * a9 29 bb bb l.ori r9,0xbbbb
1453 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1458 // l.ori r9,0xbbbb
1459 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1466 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1532 l.ori r23,r0,16
1699 l.ori r4,r5,0x80
1716 l.ori r3,r0,SPR_SR_SM