Lines Matching refs:end
103 unsigned long end, line_size;
106 end =
110 end -= line_size;
111 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
112 end -= line_size;
113 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
114 end -= line_size;
115 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
116 end -= line_size;
117 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
118 } while (end > 0);
177 unsigned long line_size, end;
180 end = start + PAGE_SIZE;
183 end -= line_size;
184 __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
185 end -= line_size;
186 __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
187 end -= line_size;
188 __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
189 end -= line_size;
190 __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
191 } while (end != start);
197 unsigned long line_size, end;
200 end = start + PAGE_SIZE;
203 end -= line_size;
204 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
205 end -= line_size;
206 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
207 end -= line_size;
208 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
209 end -= line_size;
210 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
211 } while (end != start);
217 unsigned long line_size, end;
220 end = start + PAGE_SIZE;
223 end -= line_size;
224 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
225 end -= line_size;
226 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
227 end -= line_size;
228 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
229 end -= line_size;
230 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
231 } while (end != start);
238 unsigned long line_size, end;
241 end = start + PAGE_SIZE;
244 end -= line_size;
246 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
248 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
249 end -= line_size;
251 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
253 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
254 end -= line_size;
256 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
258 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
259 end -= line_size;
261 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
263 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
264 } while (end != start);
278 void cpu_icache_inval_range(unsigned long start, unsigned long end)
284 while (end > start) {
291 void cpu_dcache_inval_range(unsigned long start, unsigned long end)
297 while (end > start) {
303 void cpu_dcache_wb_range(unsigned long start, unsigned long end)
310 while (end > start) {
318 void cpu_dcache_wbinval_range(unsigned long start, unsigned long end)
324 while (end > start) {
334 void cpu_cache_wbinval_range(unsigned long start, unsigned long end, int flushi)
340 align_end = (end + line_size - 1) & ~(line_size - 1);
346 align_end = (end + line_size - 1) & ~(line_size - 1);
352 unsigned long start, unsigned long end,
361 end = (end + line_size - 1) & ~(line_size - 1);
363 if ((end - start) > (8 * PAGE_SIZE)) {
372 t_end = ((end - 1) & PAGE_MASK);
377 cpu_dcache_wbinval_range(start, end);
379 cpu_icache_inval_range(start, end);
391 if (va_present(vma->vm_mm, end - 1)) {
393 cpu_dcache_wbinval_range(t_end, end);
395 cpu_icache_inval_range(t_end, end);
410 static inline void cpu_l2cache_op(unsigned long start, unsigned long end, unsigned long op)
414 unsigned long p_end = __pa(end);
437 #define cpu_l2cache_op(start,end,op) do { } while (0)
442 void cpu_dma_wb_range(unsigned long start, unsigned long end)
448 end = (end + line_size - 1) & (~(line_size - 1));
449 if (unlikely(start == end))
453 cpu_dcache_wb_range(start, end);
454 cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WB);
459 void cpu_dma_inval_range(unsigned long start, unsigned long end)
463 unsigned long old_end = end;
467 end = (end + line_size - 1) & (~(line_size - 1));
468 if (unlikely(start == end))
475 if (end != old_end) {
476 cpu_dcache_wbinval_range(end - line_size, end);
477 cpu_l2cache_op(end - line_size, end, CCTL_CMD_L2_PA_WBINVAL);
479 cpu_dcache_inval_range(start, end);
480 cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_INVAL);
486 void cpu_dma_wbinval_range(unsigned long start, unsigned long end)
492 end = (end + line_size - 1) & (~(line_size - 1));
493 if (unlikely(start == end))
497 cpu_dcache_wbinval_range(start, end);
498 cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WBINVAL);