Lines Matching refs:config
72 } config;
164 * Read a PCIe config space register indirectly. This is used for
192 * Write a PCIe config space register indirectly. This is used for
218 * Build a PCIe config space request address for a device
240 pcie_addr.config.upper = 2;
241 pcie_addr.config.io = 1;
242 pcie_addr.config.did = 3;
243 pcie_addr.config.subdid = 1;
244 pcie_addr.config.es = 1;
245 pcie_addr.config.port = pcie_port;
246 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
247 pcie_addr.config.bus = bus;
248 pcie_addr.config.dev = dev;
249 pcie_addr.config.func = fn;
250 pcie_addr.config.reg = reg;
255 * Read 8bits from a Device's config space
277 * Read 16bits from a Device's config space
299 * Read 32bits from a Device's config space
321 * Write 8bits to a Device's config space
340 * Write 16bits to a Device's config space
359 * Write 32bits to a Device's config space
378 * Initialize the RC config space CSRs
735 /* Allow up to 0x20 config retries */
872 /* Initialize the config space CSRs */
1309 /* Initialize the config space CSRs */
1421 * Allow config retries for 250ms. Count is based off the 5Ghz
1583 * CN55XX, and CN54XX errata with PCIe config reads from non
1585 * config read is performed that causes a UR response.
1653 * config reads from non existent devices happen