Lines Matching defs:bar1_index
705 union cvmx_npei_bar1_indexx bar1_index;
925 bar1_index.u32 = 0;
926 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
927 bar1_index.s.ca = 1; /* Not Cached */
928 bar1_index.s.end_swp = 1; /* Endian Swap mode */
929 bar1_index.s.addr_v = 1; /* Valid entry */
941 bar1_index.u32);
944 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
1162 union cvmx_pemx_bar1_indexx bar1_index;
1408 bar1_index.u64 = 0;
1409 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
1410 bar1_index.s.ca = 1; /* Not Cached */
1411 bar1_index.s.end_swp = 1; /* Endian Swap mode */
1412 bar1_index.s.addr_v = 1; /* Valid entry */
1415 cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
1417 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);