Lines Matching refs:bc
31 struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus);
33 return bc->baddr + paddr;
96 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
100 bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
101 bridge_read(bc, b_widget.w_tflush); /* Flush */
121 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
122 struct bridge_regs *bridge = bc->base;
140 bc->ioc3_sid[slot]);
158 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
159 struct bridge_regs *bridge = bc->base;
167 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
179 bc->ioc3_sid[slot]);
206 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
207 struct bridge_regs *bridge = bc->base;
245 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
246 struct bridge_regs *bridge = bc->base;
254 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
298 struct bridge_controller *bc;
315 bridge_write(data->bc, b_int_addr[pin].addr,
316 (((data->bc->intr_addr >> 30) & 0x30000) |
318 bridge_read(data->bc, b_wid_tflush);
349 data->bc = info->ctrl;
376 struct bridge_controller *bc = data->bc;
381 bridge_write(bc, b_int_addr[pin].addr,
382 (((bc->intr_addr >> 30) & 0x30000) |
384 bridge_set(bc, b_int_enable, (1 << pin));
385 bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
394 bridge_set(bc, b_int_mode, (1UL << pin));
400 device = bridge_read(bc, b_int_device);
403 bridge_write(bc, b_int_device, device);
405 bridge_read(bc, b_wid_tflush);
414 bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq));
415 bridge_read(data->bc, b_wid_tflush);
436 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
451 irq = bc->pci_int[slot][pin];
453 info.ctrl = bc;
454 info.nasid = bc->nasid;
455 info.pin = bc->int_mapping[slot][pin];
457 irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info);
461 bc->pci_int[slot][pin] = irq;
468 static void bridge_setup_ip27_baseio6g(struct bridge_controller *bc)
470 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO6G);
471 bc->ioc3_sid[6] = IOC3_SID(IOC3_SUBSYS_IP27_MIO);
472 bc->int_mapping[2][1] = 4;
473 bc->int_mapping[6][1] = 6;
476 static void bridge_setup_ip27_baseio(struct bridge_controller *bc)
478 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO);
479 bc->int_mapping[2][1] = 4;
482 static void bridge_setup_ip29_baseio(struct bridge_controller *bc)
484 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP29_SYSBOARD);
485 bc->int_mapping[2][1] = 3;
488 static void bridge_setup_ip30_sysboard(struct bridge_controller *bc)
490 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP30_SYSBOARD);
491 bc->int_mapping[2][1] = 4;
494 static void bridge_setup_menet(struct bridge_controller *bc)
496 bc->ioc3_sid[0] = IOC3_SID(IOC3_SUBSYS_MENET);
497 bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_MENET);
498 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_MENET);
499 bc->ioc3_sid[3] = IOC3_SID(IOC3_SUBSYS_MENET4);
502 static void bridge_setup_io7(struct bridge_controller *bc)
504 bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO7);
507 static void bridge_setup_io8(struct bridge_controller *bc)
509 bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO8);
512 static void bridge_setup_io9(struct bridge_controller *bc)
514 bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_IO9);
517 static void bridge_setup_ip34_fuel_sysboard(struct bridge_controller *bc)
519 bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IP34_SYSBOARD);
527 void (*setup)(struct bridge_controller *bc);
545 static void bridge_setup_board(struct bridge_controller *bc, char *partnum)
552 bridge_ioc3_devid[i].setup(bc);
610 struct bridge_controller *bc;
637 host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
643 bc = pci_host_bridge_priv(host);
645 bc->busn.name = "Bridge PCI busn";
646 bc->busn.start = 0;
647 bc->busn.end = 0xff;
648 bc->busn.flags = IORESOURCE_BUS;
650 bc->domain = domain;
654 pci_add_resource(&host->windows, &bc->busn);
660 bc->nasid = bd->nasid;
662 bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR;
663 bc->base = (struct bridge_regs *)bd->bridge_addr;
664 bc->intr_addr = bd->intr_addr;
669 bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
674 bridge_write(bc, b_int_device, 0x0);
679 bridge_clr(bc, b_wid_control,
682 bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
684 bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
691 bridge_write(bc, b_wid_int_upper,
692 ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16));
693 bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
694 bridge_write(bc, b_dir_map, (bd->masterwid << 20)); /* DMA */
695 bridge_write(bc, b_int_enable, 0);
698 bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
699 bc->pci_int[slot][0] = -1;
700 bc->pci_int[slot][1] = -1;
702 bc->int_mapping[slot][0] = slot;
703 bc->int_mapping[slot][1] = slot ^ 4;
705 bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */
707 bridge_setup_board(bc, partnum);
710 host->sysdata = bc;
738 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
739 struct fwnode_handle *fn = bc->domain->fwnode;
741 irq_domain_remove(bc->domain);