Lines Matching defs:ctx
92 static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx)
94 ctx->wired_entry = read_c0_wired();
95 add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
96 ctx->last_elo0 = ctx->last_elo1 = ~0;
102 struct alchemy_pci_context *ctx = bus->sysdata;
114 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
116 __raw_writel(r, ctx->regs + PCI_REG_STATCMD);
122 if (ctx->board_pci_idsel(device, 1) == 0) {
147 if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) {
148 mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1,
149 (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
150 ctx->last_elo0 = entryLo0;
151 ctx->last_elo1 = entryLo1;
155 __raw_writel(*data, ctx->pci_cfg_vm->addr + offset);
157 *data = __raw_readl(ctx->pci_cfg_vm->addr + offset);
164 status = __raw_readl(ctx->regs + PCI_REG_STATCMD);
175 __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD);
182 (void)ctx->board_pci_idsel(device, 0);
309 struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
310 if (!ctx)
313 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM);
314 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
315 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
316 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
317 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
318 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
319 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
320 ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID);
321 ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
322 ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM);
323 ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
324 ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
331 struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
332 if (!ctx)
335 __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM);
336 __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH);
337 __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID);
338 __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID);
339 __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV);
340 __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL);
341 __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID);
342 __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV);
343 __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM);
344 __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
345 __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
347 __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG);
353 ctx->wired_entry = 8191; /* impossibly high value */
354 alchemy_pci_wired_entry(ctx); /* install it */
365 struct alchemy_pci_context *ctx;
379 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
380 if (!ctx) {
412 ctx->regs = ioremap(r->start, resource_size(r));
413 if (!ctx->regs) {
429 ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
435 val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
437 __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
443 ctx->board_map_irq = pd->board_map_irq;
446 ctx->board_pci_idsel = pd->board_pci_idsel;
448 ctx->board_pci_idsel = alchemy_pci_def_idsel;
451 ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops;
452 ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres;
453 ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores;
461 ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
462 if (!ctx->pci_cfg_vm) {
467 ctx->wired_entry = 8191; /* impossibly high value */
468 alchemy_pci_wired_entry(ctx); /* install it */
470 set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
473 val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
477 __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
480 __alchemy_pci_ctx = ctx;
481 platform_set_drvdata(pdev, ctx);
483 register_pci_controller(&ctx->alchemy_pci_ctrl);
493 iounmap(ctx->regs);
501 kfree(ctx);
528 struct alchemy_pci_context *ctx = dev->sysdata;
529 if (ctx && ctx->board_map_irq)
530 return ctx->board_map_irq(dev, slot, pin);