Lines Matching defs:data
18 * swizzle 32bits data to return only the needed part
20 static int postprocess_read(u32 data, int where, unsigned int size)
27 ret = (data >> ((where & 3) << 3)) & 0xff;
30 ret = (data >> ((where & 3) << 3)) & 0xffff;
33 ret = data;
104 u32 data;
106 /* two phase cycle, first we write address, then read data at
112 data = le32_to_cpu(__raw_readl(pci_iospace_start));
116 *val = postprocess_read(data, where, size);
125 u32 data;
127 /* two phase cycle, first we write address, then write data to
134 data = le32_to_cpu(__raw_readl(pci_iospace_start));
135 data = preprocess_write(data, val, where, size);
137 __raw_writel(cpu_to_le32(data), pci_iospace_start);
211 u32 data;
213 data = 0;
219 data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM;
223 data = (PCI_STATUS_DEVSEL_SLOW << 16);
224 data |= fake_cb_bridge_regs.pci_command;
228 data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
232 data = (PCI_HEADER_TYPE_CARDBUS << 16);
237 data = (fake_cb_bridge_regs.bridge_control << 16);
239 data |= (0x1 << 8) | 0xff;
243 data = (fake_cb_bridge_regs.cb_latency << 24);
244 data |= (fake_cb_bridge_regs.subordinate_busn << 16);
245 data |= (fake_cb_bridge_regs.cardbus_busn << 8);
246 data |= fake_cb_bridge_regs.pci_busn;
250 data = fake_cb_bridge_regs.mem_base0;
254 data = fake_cb_bridge_regs.mem_limit0;
258 data = fake_cb_bridge_regs.mem_base1;
262 data = fake_cb_bridge_regs.mem_limit1;
267 data = fake_cb_bridge_regs.io_base0 | 0x1;
271 data = fake_cb_bridge_regs.io_limit0;
276 data = fake_cb_bridge_regs.io_base1 | 0x1;
280 data = fake_cb_bridge_regs.io_limit1;
284 *val = postprocess_read(data, where, size);
294 u32 data, tmp;
297 ret = fake_cb_bridge_read((where & ~0x3), 4, &data);
301 data = preprocess_write(data, val, where, size);
306 fake_cb_bridge_regs.pci_command = (data & 0xffff);
310 fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff;
311 fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff;
312 fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff;
313 fake_cb_bridge_regs.pci_busn = data & 0xff;
319 tmp = (data >> 16) & 0xffff;
327 fake_cb_bridge_regs.mem_base0 = data;
331 fake_cb_bridge_regs.mem_limit0 = data;
335 fake_cb_bridge_regs.mem_base1 = data;
339 fake_cb_bridge_regs.mem_limit1 = data;
343 fake_cb_bridge_regs.io_base0 = data;
347 fake_cb_bridge_regs.io_limit0 = data;
351 fake_cb_bridge_regs.io_base1 = data;
355 fake_cb_bridge_regs.io_limit1 = data;
486 u32 data;
495 data = bcm_pcie_readl(reg);
497 *val = postprocess_read(data, where, size);
506 u32 data;
516 data = bcm_pcie_readl(reg);
518 data = preprocess_write(data, val, where, size);
519 bcm_pcie_writel(data, reg);