Lines Matching refs:nlm_write_reg
142 nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,
145 nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
159 nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,
162 nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
177 nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_STATUS, 1u << vec);
179 nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
224 nlm_write_reg(md->lnkbase, status_reg, 1u << bit);
256 nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);
262 nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
269 nlm_write_reg(lnkbase, 0x1, val);
279 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32);
280 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff);
286 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val);
353 nlm_write_reg(lnkbase, 0x2C, val);
360 nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);
366 nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
373 nlm_write_reg(lnkbase, 0x1, val);
384 nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_BASE,
386 nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT,
390 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE,
392 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT,