Lines Matching defs:node
62 /* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */
113 struct nlm_soc_info *node;
227 nlm_pic_ack(md->node->picbase,
293 static int xlp_setup_msi(uint64_t lnkbase, int node, int link,
304 xirq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
306 msiaddr = MSI_LINK_ADDR(node, link);
316 nlm_setup_pic_irq(node, lirq, lirq, irt);
317 nlm_pic_init_irt(nlm_get_node(node)->picbase, irt, lirq,
318 node * nlm_threads_per_node(), 1 /*en */);
400 static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
411 xirq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
413 msixaddr = MSIX_LINK_ADDR(node, link);
448 int node, link, slot;
457 node = slot / 8;
458 lnkbase = nlm_get_pcie_base(node, link);
461 return xlp_setup_msix(lnkbase, node, link, desc);
463 return xlp_setup_msi(lnkbase, node, link, desc);
466 void __init xlp_init_node_msi_irqs(int node, int link)
472 pr_info("[%d %d] Init node PCI IRT\n", node, link);
473 nodep = nlm_get_node(node);
481 md->node = nodep;
482 md->lnkbase = nlm_get_pcie_base(node, link);
485 irq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
493 val = ((node * nlm_threads_per_node()) << 7 |
505 node * nlm_threads_per_node(), 1);
509 irq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, i));
515 void nlm_dispatch_msi(int node, int lirq)
522 irqbase = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
539 nlm_pic_ack(md->node->picbase,
542 nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
545 void nlm_dispatch_msix(int node, int lirq)
552 irqbase = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));