Lines Matching defs:lnkbase
114 uint64_t lnkbase;
142 nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,
145 nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
159 nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,
162 nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
177 nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_STATUS, 1u << vec);
179 nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
224 nlm_write_reg(md->lnkbase, status_reg, 1u << bit);
248 static void xlp_config_link_msi(uint64_t lnkbase, int lirq, uint64_t msiaddr)
253 val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);
256 nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);
259 val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
262 nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
266 val = nlm_read_reg(lnkbase, 0x1); /* CMD */
269 nlm_write_reg(lnkbase, 0x1, val);
273 val = nlm_read_pci_reg(lnkbase, 0xf);
276 nlm_write_pci_reg(lnkbase, 0xf, val);
279 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32);
280 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff);
283 val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP);
286 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val);
293 static int xlp_setup_msi(uint64_t lnkbase, int node, int link,
310 xlp_config_link_msi(lnkbase, lirq, msiaddr);
346 static void xlp_config_link_msix(uint64_t lnkbase, int lirq, uint64_t msixaddr)
350 val = nlm_read_reg(lnkbase, 0x2C);
353 nlm_write_reg(lnkbase, 0x2C, val);
357 val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);
360 nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);
363 val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
366 nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
370 val = nlm_read_reg(lnkbase, 0x1); /* CMD */
373 nlm_write_reg(lnkbase, 0x1, val);
377 val = nlm_read_pci_reg(lnkbase, 0xf);
380 nlm_write_pci_reg(lnkbase, 0xf, val);
384 nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_BASE,
386 nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT,
390 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE,
392 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT,
400 static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
418 xlp_config_link_msix(lnkbase, lirq, msixaddr);
447 uint64_t lnkbase;
458 lnkbase = nlm_get_pcie_base(node, link);
461 return xlp_setup_msix(lnkbase, node, link, desc);
463 return xlp_setup_msi(lnkbase, node, link, desc);
482 md->lnkbase = nlm_get_pcie_base(node, link);
495 nlm_write_pcie_reg(md->lnkbase, PCIE_9XX_MSIX_VECX(i +
525 status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSI_STATUS) &
528 status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) &
555 status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSIX_STATUSX(link));
557 status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS);