Lines Matching defs:dec_insn
424 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
427 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
439 regs->cp0_epc + dec_insn.pc_inc +
440 dec_insn.next_pc_inc;
460 dec_insn.pc_inc +
461 dec_insn.next_pc_inc;
470 dec_insn.pc_inc +
474 dec_insn.pc_inc +
475 dec_insn.next_pc_inc;
484 dec_insn.pc_inc +
485 dec_insn.next_pc_inc;
494 dec_insn.pc_inc +
498 dec_insn.pc_inc +
499 dec_insn.next_pc_inc;
508 dec_insn.pc_inc +
509 dec_insn.next_pc_inc;
512 *contpc = regs->cp0_epc + dec_insn.pc_inc;
527 dec_insn.pc_inc +
531 dec_insn.pc_inc +
532 dec_insn.next_pc_inc;
542 dec_insn.pc_inc +
546 dec_insn.pc_inc +
547 dec_insn.next_pc_inc;
572 dec_insn.pc_inc;
573 *contpc = regs->cp0_epc + dec_insn.pc_inc +
574 dec_insn.next_pc_inc;
580 dec_insn.pc_inc +
584 dec_insn.pc_inc +
585 dec_insn.next_pc_inc;
610 dec_insn.pc_inc;
611 *contpc = regs->cp0_epc + dec_insn.pc_inc +
612 dec_insn.next_pc_inc;
619 dec_insn.pc_inc +
623 dec_insn.pc_inc +
624 dec_insn.next_pc_inc;
632 *contpc = regs->cp0_epc + dec_insn.pc_inc +
633 dec_insn.next_pc_inc;
670 *contpc = regs->cp0_epc + dec_insn.pc_inc +
671 dec_insn.next_pc_inc;
678 *contpc = regs->cp0_epc + dec_insn.pc_inc +
679 dec_insn.next_pc_inc;
685 *contpc = regs->cp0_epc + dec_insn.pc_inc +
686 dec_insn.next_pc_inc;
694 *contpc = regs->cp0_epc + dec_insn.pc_inc +
695 dec_insn.next_pc_inc;
718 dec_insn.pc_inc +
722 dec_insn.pc_inc +
723 dec_insn.next_pc_inc;
747 dec_insn.pc_inc +
751 dec_insn.pc_inc +
752 dec_insn.next_pc_inc;
758 dec_insn.pc_inc +
762 dec_insn.pc_inc +
763 dec_insn.next_pc_inc;
972 struct mm_decoded_insn dec_insn, void __user **fault_addr)
974 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
989 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
994 if (dec_insn.micro_mips_mode) {
995 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
998 if (!isBranchInstr(xcp, dec_insn, &contpc))
1016 ir = dec_insn.next_insn; /* process delay slot instr */
1017 pc_inc = dec_insn.next_pc_inc;
1019 ir = dec_insn.insn; /* process current instr */
1020 pc_inc = dec_insn.pc_inc;
1033 if (dec_insn.micro_mips_mode) {
1246 xcp->cp0_epc += dec_insn.pc_inc;
1249 ir = dec_insn.next_insn;
1250 if (dec_insn.micro_mips_mode) {
1254 if ((dec_insn.next_pc_inc == 2) ||
1264 if (dec_insn.next_pc_inc == 2)
1339 xcp->cp0_epc += dec_insn.pc_inc;
1340 contpc += dec_insn.pc_inc;
2841 struct mm_decoded_insn dec_insn;
2874 dec_insn.insn = (*instr_ptr << 16) |
2877 dec_insn.pc_inc = 2;
2880 dec_insn.insn = (*instr_ptr << 16) |
2883 dec_insn.pc_inc = 4;
2889 dec_insn.next_insn = (*instr_ptr << 16) |
2892 dec_insn.next_pc_inc = 2;
2894 dec_insn.next_insn = (*instr_ptr << 16) |
2897 dec_insn.next_pc_inc = 4;
2899 dec_insn.micro_mips_mode = 1;
2901 if ((get_user(dec_insn.insn,
2903 (get_user(dec_insn.next_insn,
2908 dec_insn.pc_inc = 4;
2909 dec_insn.next_pc_inc = 4;
2910 dec_insn.micro_mips_mode = 0;
2913 if ((dec_insn.insn == 0) ||
2914 ((dec_insn.pc_inc == 2) &&
2915 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2916 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2922 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);